From c6566b660f8343be882cbb4fadedfa823f48e7f8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Mon, 4 Sep 2023 14:49:01 +0200
Subject: [PATCH] memlib.md: Fix typo

---
 passes/memory/memlib.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/memory/memlib.md b/passes/memory/memlib.md
index fdc2d4bed..855aa1345 100644
--- a/passes/memory/memlib.md
+++ b/passes/memory/memlib.md
@@ -267,7 +267,7 @@ The address is always `abits` wide.  If a non-narrowest width is used, the appro
 bits will be tied to 0.
 
 
-### Port `width` prooperty
+### Port `width` property
 
 If the RAM has `per_port` widths, the available width selection can be further described
 on per-port basis, by using one of the following properties: