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https://github.com/YosysHQ/yosys
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sdc: collect strictly matching objects
This commit is contained in:
Emil J. Tywoniak
parent
bfc2dfe698
commit
c615b61f9f
2 changed files with 146 additions and 101 deletions
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@ -9,6 +9,117 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SdcObjects {
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std::vector<std::string> design_ports;
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std::vector<std::pair<std::string, Cell*>> design_cells;
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std::vector<std::pair<std::string, Cell*>> design_pins;
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std::vector<std::pair<std::string, Wire*>> design_nets;
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pool<std::string> constrained_ports;
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pool<std::pair<std::string, Cell*>> constrained_cells;
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pool<std::pair<std::string, Cell*>> constrained_pins;
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pool<std::pair<std::string, Wire*>> constrained_nets;
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void sniff_module(std::list<std::string>& hierarchy, Module* mod) {
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std::string prefix;
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for (auto mod_name : hierarchy) {
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if (prefix.length())
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prefix += "/"; // TODO seperator?
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prefix += mod_name;
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}
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for (auto* wire : mod->wires()) {
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std::string name = wire->name.str();
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log_assert(name.length());
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// TODO: really skip internal wires?
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if (name[0] == '$')
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continue;
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name = name.substr(1);
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std::string path = prefix;
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if (path.length())
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path += "/";
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path += name;
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design_nets.push_back(std::make_pair(path, wire));
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}
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for (auto* cell : mod->cells()) {
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std::string name = cell->name.str();
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// TODO: really skip internal cells?
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if (name[0] == '$')
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continue;
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name = name.substr(1);
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std::string path = prefix;
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if (path.length())
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path += "/";
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path += name;
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design_cells.push_back(std::make_pair(path, cell));
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for (auto pin : cell->connections()) {
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std::string pin_name = path + "/" + pin.first.str().substr(1);
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design_pins.push_back(std::make_pair(pin_name, cell));
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}
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if (auto sub_mod = mod->design->module(cell->type)) {
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hierarchy.push_back(name);
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sniff_module(hierarchy, sub_mod);
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hierarchy.pop_back();
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}
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}
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}
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SdcObjects(Design* design) {
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Module* top = design->top_module();
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if (!top)
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log_error("Top module couldn't be determined. Check 'top' attribute usage");
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for (auto port : top->ports) {
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design_ports.push_back(port.str().substr(1));
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}
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std::list<std::string> hierarchy{};
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sniff_module(hierarchy, top);
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}
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~SdcObjects() = default;
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void dump() {
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log("Design ports:\n");
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for (auto name : design_ports) {
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log("\t%s\n", name.c_str());
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}
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log("Design cells:\n");
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for (auto [name, cell] : design_cells) {
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(void)cell;
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log("\t%s\n", name.c_str());
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}
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log("Design pins:\n");
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for (auto [name, pin] : design_pins) {
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(void)pin;
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log("\t%s\n", name.c_str());
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}
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log("Design nets:\n");
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for (auto [name, net] : design_nets) {
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(void)net;
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log("\t%s\n", name.c_str());
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}
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log("\n");
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log("Constrained ports:\n");
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for (auto name : constrained_ports) {
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log("\t%s\n", name.c_str());
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}
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log("Constrained cells:\n");
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for (auto [name, cell] : constrained_cells) {
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(void)cell;
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log("\t%s\n", name.c_str());
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}
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log("Constrained pins:\n");
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for (auto [name, pin] : constrained_pins) {
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(void)pin;
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log("\t%s\n", name.c_str());
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}
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log("Constrained nets:\n");
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for (auto [name, net] : constrained_nets) {
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(void)net;
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log("\t%s\n", name.c_str());
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}
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log("\n");
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}
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};
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template<typename T>
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static bool parse_flag(char* arg, const char* flag_name, T& flag_var) {
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std::string expected = std::string("-") + flag_name;
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@ -23,9 +134,10 @@ static bool parse_flag(char* arg, const char* flag_name, T& flag_var) {
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// TODO vectors
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// TODO cell arrays?
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static int sdc_get_pins_cmd(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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static int sdc_get_pins_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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{
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(void)interp;
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auto* objects = (SdcObjects*)data;
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// When this flag is present, the search for the pattern is made in all positions in the hierarchy.
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bool hierarchical_flag = false;
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bool regexp_flag = false;
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@ -53,9 +165,16 @@ static int sdc_get_pins_cmd(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj* c
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for (; i < objc; i++) {
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patterns.push_back(Tcl_GetString(objv[i]));
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}
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log("get_pins patterns:\n");
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for (auto pat : patterns) {
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log("\t%s\n", pat.c_str());
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bool found = false;
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for (auto [name, pin] : objects->design_pins) {
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if (name == pat) {
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found = true;
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objects->constrained_pins.insert(std::make_pair(name, pin));
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}
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}
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if (!found)
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log_warning("No matches in design for pattern %s\n", pat.c_str());
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}
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(void)hierarchical_flag;
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(void)regexp_flag;
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@ -68,9 +187,10 @@ static int sdc_get_pins_cmd(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj* c
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return TCL_OK;
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}
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static int sdc_get_ports_cmd(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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static int sdc_get_ports_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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{
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(void)interp;
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auto* objects = (SdcObjects*)data;
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bool regexp_flag = false;
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bool nocase_flag = false;
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std::vector<std::string> patterns;
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@ -84,20 +204,29 @@ static int sdc_get_ports_cmd(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj*
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for (; i < objc; i++) {
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patterns.push_back(Tcl_GetString(objv[i]));
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}
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log("get_ports patterns:\n");
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for (auto pat : patterns) {
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log("\t%s\n", pat.c_str());
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bool found = false;
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for (auto name : objects->design_ports) {
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if (name == pat) {
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found = true;
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objects->constrained_ports.insert(name);
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}
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}
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if (!found)
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log_warning("No matches in design for pattern %s\n", pat.c_str());
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}
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(void)regexp_flag;
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(void)nocase_flag;
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return TCL_OK;
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}
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class SDCInterpreter
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{
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private:
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Tcl_Interp* interp = nullptr;
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public:
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std::unique_ptr<SdcObjects> objects;
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~SDCInterpreter() {
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if (interp)
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Tcl_DeleteInterp(interp);
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@ -106,105 +235,21 @@ public:
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static SDCInterpreter instance;
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return instance;
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}
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Tcl_Interp* fresh_interp() {
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Tcl_Interp* fresh_interp(Design* design) {
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if (interp)
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Tcl_DeleteInterp(interp);
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interp = Tcl_CreateInterp();
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if (Tcl_Init(interp)!=TCL_OK)
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log_warning("Tcl_Init() call failed - %s\n",Tcl_ErrnoMsg(Tcl_GetErrno()));
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Tcl_CreateObjCommand(interp, "get_pins", sdc_get_pins_cmd, NULL, NULL);
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Tcl_CreateObjCommand(interp, "get_ports", sdc_get_ports_cmd, NULL, NULL);
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log_error("Tcl_Init() call failed - %s\n",Tcl_ErrnoMsg(Tcl_GetErrno()));
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objects = std::make_unique<SdcObjects>(design);
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Tcl_CreateObjCommand(interp, "get_pins", sdc_get_pins_cmd, (ClientData) objects.get(), NULL);
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Tcl_CreateObjCommand(interp, "get_ports", sdc_get_ports_cmd, (ClientData) objects.get(), NULL);
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return interp;
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}
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};
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struct SdcObjects {
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std::vector<std::string> ports;
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std::vector<std::pair<std::string, Cell*>> cells;
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std::vector<std::pair<std::string, Cell*>> pins;
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std::vector<std::pair<std::string, Wire*>> nets;
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void sniff_module(std::list<std::string>& hierarchy, Module* mod) {
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log_debug("sniffing module %s\n", mod->name.c_str());
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std::string prefix;
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for (auto mod_name : hierarchy) {
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if (prefix.length())
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prefix += "/"; // TODO seperator?
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prefix += mod_name;
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}
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for (auto* wire : mod->wires()) {
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std::string name = wire->name.str();
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log_assert(name.length());
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// TODO: really skip internal wires?
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if (name[0] == '$')
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continue;
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name = name.substr(1);
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std::string path = prefix;
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if (path.length())
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path += "/";
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path += name;
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nets.push_back(std::make_pair(path, wire));
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}
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for (auto* cell : mod->cells()) {
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std::string name = cell->name.str();
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// TODO: really skip internal cells?
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if (name[0] == '$')
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continue;
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name = name.substr(1);
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std::string path = prefix;
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if (path.length())
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path += "/";
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path += name;
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cells.push_back(std::make_pair(path, cell));
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for (auto pin : cell->connections()) {
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std::string pin_name = path + "/" + pin.first.str().substr(1);
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pins.push_back(std::make_pair(pin_name, cell));
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}
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if (auto sub_mod = mod->design->module(cell->type)) {
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hierarchy.push_back(name);
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sniff_module(hierarchy, sub_mod);
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hierarchy.pop_back();
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}
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}
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}
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SdcObjects(Design* design) {
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Module* top = design->top_module();
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if (!top)
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log_error("Top module couldn't be determined. Check 'top' attribute usage");
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for (auto port : top->ports) {
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ports.push_back(port.str().substr(1));
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}
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std::list<std::string> hierarchy{};
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sniff_module(hierarchy, top);
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}
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void dump() {
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log("Dumping detected design objects visible to SDC constraints\n");
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log("Ports:\n");
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for (auto name : ports) {
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log("\t%s\n", name.c_str());
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}
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log("Cells:\n");
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for (auto [name, cell] : cells) {
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(void)cell;
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log("\t%s\n", name.c_str());
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}
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log("Pins:\n");
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for (auto [name, pin] : pins) {
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(void)pin;
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log("\t%s\n", name.c_str());
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}
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log("Nets:\n");
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for (auto [name, net] : nets) {
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(void)net;
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log("\t%s\n", name.c_str());
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}
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log("\n");
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}
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};
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// Also see TclPass
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struct SdcPass : public Pass {
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// TODO help
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@ -213,16 +258,16 @@ struct SdcPass : public Pass {
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if (args.size() < 2)
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log_cmd_error("Missing SDC file.\n");
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// TODO optional extra stub file
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Tcl_Interp *interp = SDCInterpreter::get().fresh_interp();
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SDCInterpreter& sdc = SDCInterpreter::get();
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Tcl_Interp *interp = sdc.fresh_interp(design);
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Tcl_Preserve(interp);
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std::string stub_path = "+/sdc/stubs.sdc";
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rewrite_filename(stub_path);
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SdcObjects objects(design);
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objects.dump();
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if (Tcl_EvalFile(interp, stub_path.c_str()) != TCL_OK)
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log_cmd_error("SDC interpreter returned an error in stub file: %s\n", Tcl_GetStringResult(interp));
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if (Tcl_EvalFile(interp, args[1].c_str()) != TCL_OK)
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log_cmd_error("SDC interpreter returned an error: %s\n", Tcl_GetStringResult(interp));
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sdc.objects->dump();
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Tcl_Release(interp);
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}
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} SdcPass;
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@ -1,5 +1,5 @@
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puts "SDC constraints file says hello from arbitrary Tcl execution"
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set_false_path -from [get_pins s1/sa] -to [get_pins s1/sb]
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puts "This should print something:"
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puts [get_ports {slink_clk_o slink_*_o}]
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puts [get_ports a b]
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puts "Did it?"
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