mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
macc_v2: Start new cell
This commit is contained in:
parent
08394c51a2
commit
c5fd96ebb0
5 changed files with 119 additions and 37 deletions
|
@ -1467,6 +1467,30 @@ namespace {
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($macc_v2)) {
|
||||
if (param(ID::NTERMS) <= 0)
|
||||
error(__LINE__);
|
||||
param_bits(ID::TERM_NEGATED, param(ID::NTERMS));
|
||||
param_bits(ID::A_SIGNED, param(ID::NTERMS));
|
||||
param_bits(ID::B_SIGNED, param(ID::NTERMS));
|
||||
if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED))
|
||||
error(__LINE__);
|
||||
param_bits(ID::A_WIDTHS, param(ID::NTERMS) * 16);
|
||||
param_bits(ID::B_WIDTHS, param(ID::NTERMS) * 16);
|
||||
const Const &a_width = cell->getParam(ID::A_WIDTHS);
|
||||
const Const &b_width = cell->getParam(ID::B_WIDTHS);
|
||||
int a_width_sum = 0, b_width_sum = 0;
|
||||
for (int i = 0; i < param(ID::NTERMS); i++) {
|
||||
a_width_sum += a_width.extract(16 * i, 16).as_int(false);
|
||||
b_width_sum += b_width.extract(16 * i, 16).as_int(false);
|
||||
}
|
||||
port(ID::A, a_width_sum);
|
||||
port(ID::B, b_width_sum);
|
||||
port(ID::Y, param(ID::Y_WIDTH));
|
||||
check_expected();
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type == ID($logic_not)) {
|
||||
param_bool(ID::A_SIGNED);
|
||||
port(ID::A, param(ID::A_WIDTH));
|
||||
|
@ -4099,6 +4123,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
|
|||
return;
|
||||
}
|
||||
|
||||
if (type == ID($macc_v2)) {
|
||||
parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
|
||||
return;
|
||||
}
|
||||
|
||||
bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
|
||||
|
||||
if (connections_.count(ID::A)) {
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue