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adffs test update (equiv_opt -multiclock). div_mod test fix

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SergeyDegtyar 2019-09-17 12:19:31 +03:00
parent 93f305b1c5
commit c597c2f2ae
3 changed files with 12 additions and 17 deletions
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5
tests/ecp5/adffs.ys
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@ -1,10 +1,9 @@
read_verilog adffs.v
proc
async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:TRELLIS_FF
select -assert-count 7 t:LUT4
select -assert-count 3 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D