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liberty: Test non-ascii characters

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Emil J. Tywoniak 2025-04-17 00:17:06 +02:00
parent ce74404890
commit c555add231
3 changed files with 31 additions and 0 deletions
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tests/liberty/non-ascii.lib.verilogsim.ok Normal file
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module buffer (A, Y);
input A;
output Y;
assign Y = A; // "A"
endmodule