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abc9_ops: more robust

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This commit is contained in:
Eddie Hung 2020-04-15 15:50:57 -07:00
parent 8d7b3c06b2
commit c52bb11fb6
1 changed files with 14 additions and 8 deletions
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22
passes/techmap/abc9_ops.cc
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@ -641,7 +641,8 @@ void prep_box(RTLIL::Design *design)
log_assert(num_outputs == 1); log_assert(num_outputs == 1);
ss << log_id(module) << " " << r.first->second.as_int(); ss << log_id(module) << " " << r.first->second.as_int();
ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); log_assert(module->get_bool_attribute(ID::whitebox));
ss << " " << "1";
ss << " " << num_inputs << " " << num_outputs << std::endl; ss << " " << num_inputs << " " << num_outputs << std::endl;
ss << "#"; ss << "#";
@ -659,6 +660,9 @@ void prep_box(RTLIL::Design *design)
ss << std::endl; ss << std::endl;
auto &t = timing.setup_module(module).required; auto &t = timing.setup_module(module).required;
if (t.empty())
log_error("Module '%s' with (* abc9_flop *) has no clk-to-q timing (and thus no connectivity) information.\n", log_id(module));
first = true; first = true;
for (auto port_name : module->ports) { for (auto port_name : module->ports) {
auto wire = module->wire(port_name); auto wire = module->wire(port_name);
@ -671,8 +675,8 @@ void prep_box(RTLIL::Design *design)
log_assert(GetSize(wire) == 1); log_assert(GetSize(wire) == 1);
auto it = t.find(TimingInfo::NameBit(port_name,0)); auto it = t.find(TimingInfo::NameBit(port_name,0));
if (it == t.end()) if (it == t.end())
// Assume that no setup time means zero // Assume no connectivity if no setup time
ss << 0; ss << "-";
else { else {
ss << it->second; ss << it->second;
@ -743,9 +747,11 @@ void prep_box(RTLIL::Design *design)
} }
ss << std::endl; ss << std::endl;
auto &t = timing.setup_module(module).comb; auto &t = timing.setup_module(module);
if (t.empty()) if (t.comb.empty())
log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module)); log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", log_id(module));
if (!t.arrival.empty() || !t.required.empty())
log_error("Module '%s' with (* abc9_box *) has setup and/or edge-sensitive timing information.\n", log_id(module));
for (const auto &o : outputs) { for (const auto &o : outputs) {
first = true; first = true;
@ -754,8 +760,8 @@ void prep_box(RTLIL::Design *design)
first = false; first = false;
else else
ss << " "; ss << " ";
auto jt = t.find(TimingInfo::BitBit(i,o)); auto jt = t.comb.find(TimingInfo::BitBit(i,o));
if (jt == t.end()) if (jt == t.comb.end())
ss << "-"; ss << "-";
else else
ss << jt->second; ss << jt->second;