3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-26 04:56:05 +00:00

Documentation improvements etc.

- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
This commit is contained in:
Ruben Undheim 2018-10-13 20:34:44 +02:00
parent a36d1701dd
commit c50afc4246
5 changed files with 77 additions and 38 deletions

View file

@ -452,6 +452,9 @@ from SystemVerilog:
into a design with ``read_verilog``, all its packages are available to
SystemVerilog files being read into the same design afterwards.
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
Building the documentation
==========================