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Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
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@ -452,6 +452,9 @@ from SystemVerilog:
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into a design with ``read_verilog``, all its packages are available to
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SystemVerilog files being read into the same design afterwards.
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- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
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ports are inputs or outputs are supported.
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Building the documentation
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==========================
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