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dfflibmap: fix formal verilog test so that it actually maps all flops

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Emil J. Tywoniak 2026-07-27 22:08:39 +02:00
parent 1a1d9494da
commit c50290fdab
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tests/techmap/dfflibmap_proc_formal.ys
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@ -44,6 +44,7 @@ EOT
proc
opt
techmap
copy top top_unmapped
design -save start