mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-06 11:20:27 +00:00
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
This commit is contained in:
parent
a5764a1236
commit
c4d37813cb
2 changed files with 6 additions and 6 deletions
|
@ -78,7 +78,7 @@ bram $__XILINX_RAM64X3SDP
|
|||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM32M
|
||||
bram $__XILINX_RAM32X2Q
|
||||
init 1
|
||||
abits 5
|
||||
dbits 2
|
||||
|
@ -91,7 +91,7 @@ bram $__XILINX_RAM32M
|
|||
clkpol 0 2
|
||||
endbram
|
||||
|
||||
bram $__XILINX_RAM64M
|
||||
bram $__XILINX_RAM64X1Q
|
||||
init 1
|
||||
abits 6
|
||||
dbits 1
|
||||
|
@ -151,7 +151,7 @@ match $__XILINX_RAM64X3SDP
|
|||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM32M
|
||||
match $__XILINX_RAM32X2Q
|
||||
min bits 5
|
||||
min rports 3
|
||||
min wports 1
|
||||
|
@ -159,7 +159,7 @@ match $__XILINX_RAM32M
|
|||
or_next_if_better
|
||||
endmatch
|
||||
|
||||
match $__XILINX_RAM64M
|
||||
match $__XILINX_RAM64X1Q
|
||||
min bits 5
|
||||
min rports 3
|
||||
min wports 1
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue