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Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog

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tests: Check that Icarus can parse arch sim models
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Eddie Hung 2019-06-27 12:31:15 -07:00 • committed by GitHub
commit c4c39e9814
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2 changed files with 19 additions and 0 deletions
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1
Makefile
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@ -681,6 +681,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
+cd tests/opt && bash run-test.sh +cd tests/opt && bash run-test.sh
+cd tests/aiger && bash run-test.sh +cd tests/aiger && bash run-test.sh
+cd tests/arch && bash run-test.sh
@echo "" @echo ""
@echo " Passed \"make test\"." @echo " Passed \"make test\"."
@echo "" @echo ""

18
tests/arch/run-test.sh Executable file
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@ -0,0 +1,18 @@
#!/bin/bash
set -e
echo "Running syntax check on arch sim models"
for arch in ../../techlibs/*; do
find $arch -name cells_sim.v | while read path; do
echo -n "Test $path ->"
iverilog -t null -I$arch $path
echo " ok"
done
done
for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
echo -n "Test $path ->"
iverilog -t null $path
echo " ok"
done