mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Added proper Design->addModule interface

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 21:12:09 +02:00
parent 5da343b7de
commit c4bdba78cb
3 changed files with 43 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

7
kernel/rtlil.h
View file

@ -350,7 +350,12 @@ struct RTLIL::Design
~Design();
RTLIL::ObjRange<RTLIL::Module*> modules() { return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_); }
RTLIL::ObjRange<RTLIL::Module*> modules();
RTLIL::Module *module(RTLIL::IdString name);
void add(RTLIL::Module *module);
RTLIL::Module *addModule(RTLIL::IdString name);
void remove(RTLIL::Module *module);
void check();
void optimize();