mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Release version 0.51

Browse source
This commit is contained in:
Miodrag Milanovic 2025-03-12 08:31:37 +01:00
parent 81639073a3
commit c4b5190229
3 changed files with 18 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

16
CHANGELOG
View file

@ -2,8 +2,22 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.50 .. Yosys 0.51-dev
Yosys 0.50 .. Yosys 0.51
--------------------------
* New commands and options
- Added "abstract" pass to allow reducing and never increasing
the constraints on a circuit's behavior in a formal verification setting.
* Various
- "splitcells" pass now splits "aldff" cells.
- FunctionalIR documentation
* QuickLogic support
- Added IOFF inference for qlf_k6n10f
* Intel support
- Fixed RAM and DSP support.
- Overall performance improvement for "synth_intel".
Yosys 0.49 .. Yosys 0.50
--------------------------