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Create a single-port URAM mapping to support memories 2048 x 144b

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Adrien Prost-Boucle 2025-05-09 14:16:03 +02:00
parent f60bbe64ac
commit c4a49f0c55
2 changed files with 161 additions and 0 deletions
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23
techlibs/xilinx/urams.txt
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@ -35,3 +35,26 @@ ram huge $__XILINX_URAM_ {
wrbe_separate;
}
}
ram huge $__XILINX_URAM_SP_ {
abits 11;
width 144;
cost 1024;
option "BYTEWIDTH" 8 byte 8;
option "BYTEWIDTH" 9 byte 9;
init zero;
port srsw "A" {
clock anyedge "C";
clken;
rdwr no_change;
rdinit zero;
portoption "RST_MODE" "SYNC" {
rdsrst zero ungated;
}
portoption "RST_MODE" "ASYNC" {
rdarst zero;
}
wrtrans all new;
wrbe_separate;
}
}