mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-16 22:51:28 +00:00
Merge pull request #5304 from rocallahan/idstring-stringf
Support `IdString` parameters in `stringf()` and remove `.c_str()` in a lot of places
This commit is contained in:
commit
c468ee7add
92 changed files with 807 additions and 775 deletions
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@ -126,14 +126,14 @@ struct BugpointPass : public Pass {
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string bugpoint_file = "bugpoint-case";
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if (suffix.size())
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bugpoint_file += stringf(".%.8s", suffix.c_str());
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bugpoint_file += stringf(".%.8s", suffix);
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std::ofstream f(bugpoint_file + ".il");
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RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false);
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f.close();
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string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner.c_str(), yosys_cmd.c_str(), bugpoint_file.c_str(), yosys_arg.c_str(), bugpoint_file.c_str());
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if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file.c_str());
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string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner, yosys_cmd, bugpoint_file, yosys_arg, bugpoint_file);
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if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file);
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auto status = run_command(yosys_cmdline);
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// we're not processing lines, which means we're getting raw system() returns
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if(WIFEXITED(status))
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@ -156,7 +156,7 @@ struct BugpointPass : public Pass {
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string bugpoint_file = "bugpoint-case";
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if (suffix.size())
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bugpoint_file += stringf(".%.8s", suffix.c_str());
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bugpoint_file += stringf(".%.8s", suffix);
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bugpoint_file += err ? ".err" : ".log";
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std::ifstream f(bugpoint_file);
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@ -469,13 +469,13 @@ struct BugpointPass : public Pass {
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if (args[argidx] == "-script" && argidx + 1 < args.size()) {
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if (!yosys_arg.empty())
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log_cmd_error("A -script or -command option can be only provided once!\n");
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yosys_arg = stringf("-s %s", args[++argidx].c_str());
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yosys_arg = stringf("-s %s", args[++argidx]);
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continue;
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}
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if (args[argidx] == "-command" && argidx + 1 < args.size()) {
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if (!yosys_arg.empty())
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log_cmd_error("A -script or -command option can be only provided once!\n");
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yosys_arg = stringf("-p %s", args[++argidx].c_str());
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yosys_arg = stringf("-p %s", args[++argidx]);
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continue;
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}
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if (args[argidx] == "-grep" && argidx + 1 < args.size()) {
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@ -322,7 +322,7 @@ struct CheckPass : public Pass {
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if (wire_drivers.count(state)) {
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string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state));
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for (auto str : wire_drivers[state])
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message += stringf(" %s\n", str.c_str());
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message += stringf(" %s\n", str);
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log_warning("%s", message.c_str());
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counter++;
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}
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@ -331,7 +331,7 @@ struct CheckPass : public Pass {
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if (wire_drivers_count[it.first] > 1) {
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string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
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for (auto str : it.second)
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message += stringf(" %s\n", str.c_str());
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message += stringf(" %s\n", str);
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log_warning("%s", message.c_str());
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counter++;
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}
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@ -394,10 +394,10 @@ struct CheckPass : public Pass {
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std::string driver_src;
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if (driver->has_attribute(ID::src)) {
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std::string src_attr = driver->get_src_attribute();
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driver_src = stringf(" source: %s", src_attr.c_str());
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driver_src = stringf(" source: %s", src_attr);
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}
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message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str());
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message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src);
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if (!coarsened_cells.count(driver)) {
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MatchingEdgePrinter printer(message, sigmap, prev, bit);
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@ -411,9 +411,9 @@ struct CheckPass : public Pass {
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std::string wire_src;
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if (wire->has_attribute(ID::src)) {
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std::string src_attr = wire->get_src_attribute();
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wire_src = stringf(" source: %s", src_attr.c_str());
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wire_src = stringf(" source: %s", src_attr);
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}
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message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src.c_str());
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message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src);
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}
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prev = bit;
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@ -372,7 +372,7 @@ struct DftTagWorker {
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void propagate_tags(Cell *cell)
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{
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if (cell->type == ID($set_tag)) {
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
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if (all_tags.insert(tag).second) {
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auto group_sep = tag.str().find(':');
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IdString tag_group = group_sep != std::string::npos ? tag.str().substr(0, group_sep) : tag;
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@ -478,7 +478,7 @@ struct DftTagWorker {
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void process_cell(IdString tag, Cell *cell)
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{
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if (cell->type == ID($set_tag)) {
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IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
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IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
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auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
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auto &sig_y = cell->getPort(ID::Y);
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@ -752,7 +752,7 @@ struct DftTagWorker {
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for (auto cell : get_tag_cells) {
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auto &sig_a = cell->getPort(ID::A);
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
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tag_signal(tag, sig_a);
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}
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@ -772,7 +772,7 @@ struct DftTagWorker {
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continue;
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int index = 0;
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auto name = module->uniquify(stringf("%s:%s", wire->name.c_str(), tag.c_str() + 1), index);
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auto name = module->uniquify(stringf("%s:%s", wire->name, tag.c_str() + 1), index);
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auto hdlname = wire->get_hdlname_attribute();
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if (!hdlname.empty())
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@ -817,7 +817,7 @@ struct DftTagWorker {
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for (auto cell : get_tag_cells) {
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auto &sig_a = cell->getPort(ID::A);
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auto &sig_y = cell->getPort(ID::Y);
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
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auto tag_sig = tag_signal(tag, sig_a);
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module->connect(sig_y, tag_sig);
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@ -163,7 +163,7 @@ private:
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std::vector<RTLIL::SigSpec> next_pmux_y_ports, pmux_y_ports(costs.begin(), costs.begin() + exp2(select_width));
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for (auto i = 0; pmux_y_ports.size() > 1; ++i) {
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for (auto j = 0; j+1 < GetSize(pmux_y_ports); j += 2) {
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next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name.c_str(), i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->get_src_attribute()));
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next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name, i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->get_src_attribute()));
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}
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if (GetSize(pmux_y_ports) % 2 == 1)
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next_pmux_y_ports.push_back(pmux_y_ports[GetSize(pmux_y_ports) - 1]);
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@ -206,7 +206,7 @@ private:
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int num_versions = opt_instrumentmore? 8 : 4;
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for (auto i = 1; i <= num_versions; ++i)
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taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name.c_str(), i), 1)));
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taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1)));
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for (auto i = 0; i < num_versions; ++i) {
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switch(i) {
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@ -239,7 +239,7 @@ private:
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std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
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for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) {
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for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) {
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next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name.c_str(), i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
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next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
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}
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if (GetSize(meta_mux_y_ports) % 2 == 1)
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next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]);
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@ -271,7 +271,7 @@ private:
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log_assert(exp2(select_width) == num_versions);
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for (auto i = 1; i <= num_versions; ++i)
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taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name.c_str(), i), 1)));
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taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1)));
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for (auto i = 0; i < num_versions; ++i) {
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switch(i) {
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@ -294,7 +294,7 @@ private:
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std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
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for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) {
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for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) {
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next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name.c_str(), i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
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next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
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}
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if (GetSize(meta_mux_y_ports) % 2 == 1)
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next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]);
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@ -243,7 +243,7 @@ struct PortarcsPass : Pass {
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if (draw_mode) {
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auto bit_str = [](SigBit bit) {
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return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()).c_str(), bit.offset);
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return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset);
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};
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std::vector<std::string> headings;
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@ -64,7 +64,7 @@ static std::string derive_name_from_src(const std::string &src, int counter)
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if (src_base.empty())
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return stringf("$%d", counter);
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else
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return stringf("\\%s$%d", src_base.c_str(), counter);
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return stringf("\\%s$%d", src_base, counter);
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}
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static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, string suffix, bool move_to_cell)
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@ -422,7 +422,7 @@ struct RenamePass : public Pass {
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if (wire_suffix.empty()) {
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for (auto const &[port, _] : cell->connections()) {
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if (cell->output(port)) {
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wire_suffix += stringf("%s.%s", cell->type.c_str(), port.c_str() + 1);
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wire_suffix += stringf("%s.%s", cell->type, port.c_str() + 1);
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break;
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}
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}
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@ -449,7 +449,7 @@ struct RenamePass : public Pass {
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for (auto wire : module->selected_wires())
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if (wire->name[0] == '$') {
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RTLIL::IdString buf;
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do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix);
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while (module->wire(buf) != nullptr);
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new_wire_names[wire] = buf;
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}
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@ -457,7 +457,7 @@ struct RenamePass : public Pass {
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for (auto cell : module->selected_cells())
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if (cell->name[0] == '$') {
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RTLIL::IdString buf;
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do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
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do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix);
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while (module->cell(buf) != nullptr);
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new_cell_names[cell] = buf;
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}
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@ -149,7 +149,7 @@ struct ShowWorker
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{
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for (auto &s : color_selections)
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if (s.second.selected_member(module->name, member_name)) {
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return stringf("color=\"%s\", fontcolor=\"%s\"", s.first.c_str(), s.first.c_str());
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return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
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}
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RTLIL::Const colorattr_value;
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@ -308,11 +308,11 @@ struct ShowWorker
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std::string repinfo = rep > 1 ? stringf("%dx ", rep) : "";
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std::string portside = stringf("%d:%d", bitpos, bitpos - rep*c.width + 1);
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std::string remoteside = stringf("%s%d:%d", repinfo.c_str(), cl, cr);
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std::string remoteside = stringf("%s%d:%d", repinfo, cl, cr);
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if (driver) {
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log_assert(!net.empty());
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label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, portside.c_str(), remoteside.c_str()));
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label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, portside, remoteside));
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net_conn_map[net].in.insert({stringf("x%d:s%d", dot_idx, chunk_idx), rep*c.width});
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net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
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} else {
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@ -325,7 +325,7 @@ struct ShowWorker
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c.data.front() == State::Sz ? 'Z' : '?',
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bitpos, bitpos-rep*c.width+1));
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} else {
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label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, remoteside.c_str(), portside.c_str()));
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label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, remoteside, portside));
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net_conn_map[net].out.insert({stringf("x%d:s%d", dot_idx, chunk_idx), rep*c.width});
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net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
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}
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@ -335,14 +335,14 @@ struct ShowWorker
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}
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code += stringf("x%d [ shape=record, style=rounded, label=\"", dot_idx) \
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+ join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig).c_str());
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+ join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig));
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if (!port.empty()) {
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currentColor = xorshift32(currentColor);
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if (driver)
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code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), dot_idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
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code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port, dot_idx, nextColor(sig), widthLabel(sig.size()));
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else
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code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", dot_idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
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code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", dot_idx, port, nextColor(sig), widthLabel(sig.size()));
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}
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if (node != nullptr)
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*node = stringf("x%d", dot_idx);
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@ -490,7 +490,7 @@ struct ShowWorker
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std::string in_label = join_label_pieces(in_label_pieces);
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std::string out_label = join_label_pieces(out_label_pieces);
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std::string label_string = stringf("{{%s}|%s\\n%s|{%s}}", in_label.c_str(),
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std::string label_string = stringf("{{%s}|%s\\n%s|{%s}}", in_label,
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findLabel(cell->name.str()), escape(cell->type.str()),
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out_label.c_str());
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@ -904,8 +904,8 @@ struct ShowPass : public Pass {
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if (libs.size() > 0)
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log_header(design, "Continuing show pass.\n");
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std::string dot_file = stringf("%s.dot", prefix.c_str());
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std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());
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std::string dot_file = stringf("%s.dot", prefix);
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std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
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log("Writing dot description to `%s'.\n", dot_file.c_str());
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FILE *f = fopen(dot_file.c_str(), "w");
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@ -932,7 +932,7 @@ struct ShowPass : public Pass {
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#else
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#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
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#endif
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std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
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std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
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#undef DOT_CMD
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log("Exec: %s\n", cmd.c_str());
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#if !defined(YOSYS_DISABLE_SPAWN)
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@ -950,9 +950,9 @@ struct ShowPass : public Pass {
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// system()/cmd.exe does not understand single quotes nor
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||||
// background tasks on Windows. So we have to pause yosys
|
||||
// until the viewer exits.
|
||||
std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str());
|
||||
std::string cmd = stringf("%s \"%s\"", viewer_exe, out_file);
|
||||
#else
|
||||
std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str());
|
||||
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
|
||||
#endif
|
||||
log("Exec: %s\n", cmd.c_str());
|
||||
if (run_command(cmd) != 0)
|
||||
|
@ -960,9 +960,9 @@ struct ShowPass : public Pass {
|
|||
} else
|
||||
if (format.empty()) {
|
||||
#ifdef __APPLE__
|
||||
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
|
||||
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file, dot_file, background);
|
||||
#else
|
||||
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
|
||||
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
|
||||
#endif
|
||||
log("Exec: %s\n", cmd.c_str());
|
||||
if (run_command(cmd) != 0)
|
||||
|
|
|
@ -193,19 +193,19 @@ struct statdata_t {
|
|||
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
|
||||
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
|
||||
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
|
||||
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
|
||||
cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
|
||||
} else if (cell_type.in(ID($mux)))
|
||||
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)));
|
||||
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y)));
|
||||
else if (cell_type.in(ID($bmux), ID($pmux)))
|
||||
cell_type =
|
||||
stringf("%s_%d_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
|
||||
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
|
||||
else if (cell_type == ID($demux))
|
||||
cell_type =
|
||||
stringf("%s_%d_%d", cell_type.c_str(), GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
|
||||
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
|
||||
else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
|
||||
ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
|
||||
ID($dlatchsr)))
|
||||
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
|
||||
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q)));
|
||||
}
|
||||
|
||||
if (!cell_area.empty()) {
|
||||
|
|
|
@ -320,7 +320,7 @@ struct EstimateSta {
|
|||
std::string cell_src;
|
||||
if (cell->has_attribute(ID::src)) {
|
||||
std::string src_attr = cell->get_src_attribute();
|
||||
cell_src = stringf(" source: %s", src_attr.c_str());
|
||||
cell_src = stringf(" source: %s", src_attr);
|
||||
}
|
||||
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str());
|
||||
printed.insert(cell);
|
||||
|
@ -331,7 +331,7 @@ struct EstimateSta {
|
|||
std::string wire_src;
|
||||
if (bit.wire && bit.wire->has_attribute(ID::src)) {
|
||||
std::string src_attr = bit.wire->get_src_attribute();
|
||||
wire_src = stringf(" source: %s", src_attr.c_str());
|
||||
wire_src = stringf(" source: %s", src_attr);
|
||||
}
|
||||
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]);
|
||||
}
|
||||
|
|
|
@ -982,8 +982,8 @@ struct VizPass : public Pass {
|
|||
if (modlist.empty())
|
||||
log_cmd_error("Nothing there to show.\n");
|
||||
|
||||
std::string dot_file = stringf("%s.dot", prefix.c_str());
|
||||
std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());
|
||||
std::string dot_file = stringf("%s.dot", prefix);
|
||||
std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
|
||||
|
||||
if (custom_prefix)
|
||||
yosys_output_files.insert(dot_file);
|
||||
|
@ -1026,7 +1026,7 @@ struct VizPass : public Pass {
|
|||
#else
|
||||
#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
|
||||
#endif
|
||||
std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
|
||||
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
|
||||
#undef DOT_CMD
|
||||
log("Exec: %s\n", cmd.c_str());
|
||||
#if !defined(YOSYS_DISABLE_SPAWN)
|
||||
|
@ -1043,9 +1043,9 @@ struct VizPass : public Pass {
|
|||
// system()/cmd.exe does not understand single quotes nor
|
||||
// background tasks on Windows. So we have to pause yosys
|
||||
// until the viewer exits.
|
||||
std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str());
|
||||
std::string cmd = stringf("%s \"%s\"", viewer_exe, out_file);
|
||||
#else
|
||||
std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str());
|
||||
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
|
||||
#endif
|
||||
log("Exec: %s\n", cmd.c_str());
|
||||
if (run_command(cmd) != 0)
|
||||
|
@ -1053,9 +1053,9 @@ struct VizPass : public Pass {
|
|||
} else
|
||||
if (format.empty()) {
|
||||
#ifdef __APPLE__
|
||||
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
|
||||
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file, dot_file, background);
|
||||
#else
|
||||
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
|
||||
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
|
||||
#endif
|
||||
log("Exec: %s\n", cmd.c_str());
|
||||
if (run_command(cmd) != 0)
|
||||
|
|
|
@ -97,9 +97,9 @@ struct Chunk {
|
|||
if (len == cell->getPort(port).size())
|
||||
return port;
|
||||
else if (len == 1)
|
||||
return stringf("%s[%d]", port.c_str(), base);
|
||||
return stringf("%s[%d]", port, base);
|
||||
else
|
||||
return stringf("%s[%d:%d]", port.c_str(), base + len - 1, base);
|
||||
return stringf("%s[%d:%d]", port, base + len - 1, base);
|
||||
}
|
||||
|
||||
SigSpec sample(Cell *cell)
|
||||
|
|
|
@ -978,8 +978,8 @@ struct XpropWorker
|
|||
if (wire->port_input == wire->port_output) {
|
||||
log_warning("Port %s not an input or an output port which is not supported by xprop\n", log_id(wire));
|
||||
} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
|
||||
auto port_d = module->uniquify(stringf("%s_d", port.c_str()));
|
||||
auto port_x = module->uniquify(stringf("%s_x", port.c_str()));
|
||||
auto port_d = module->uniquify(stringf("%s_d", port));
|
||||
auto port_x = module->uniquify(stringf("%s_x", port));
|
||||
|
||||
auto wire_d = module->addWire(port_d, GetSize(wire));
|
||||
auto wire_x = module->addWire(port_x, GetSize(wire));
|
||||
|
@ -1031,8 +1031,8 @@ struct XpropWorker
|
|||
continue;
|
||||
int index_d = 0;
|
||||
int index_x = 0;
|
||||
auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()), index_d);
|
||||
auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()), index_x);
|
||||
auto name_d = module->uniquify(stringf("%s_d", wire->name), index_d);
|
||||
auto name_x = module->uniquify(stringf("%s_x", wire->name), index_x);
|
||||
|
||||
auto hdlname = wire->get_hdlname_attribute();
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue