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Merge pull request #5304 from rocallahan/idstring-stringf

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Support `IdString` parameters in `stringf()` and remove `.c_str()` in a lot of places
This commit is contained in:
Jannis Harder 2025-09-08 20:29:20 +02:00 • committed by GitHub
commit c468ee7add
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GPG key ID: B5690EEEBB952194
92 changed files with 807 additions and 775 deletions
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12
passes/cmds/bugpoint.cc
View file

@ -126,14 +126,14 @@ struct BugpointPass : public Pass {
string bugpoint_file = "bugpoint-case";
if (suffix.size())
bugpoint_file += stringf(".%.8s", suffix.c_str());
bugpoint_file += stringf(".%.8s", suffix);
std::ofstream f(bugpoint_file + ".il");
RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false);
f.close();
string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner.c_str(), yosys_cmd.c_str(), bugpoint_file.c_str(), yosys_arg.c_str(), bugpoint_file.c_str());
if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file.c_str());
string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner, yosys_cmd, bugpoint_file, yosys_arg, bugpoint_file);
if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file);
auto status = run_command(yosys_cmdline);
// we're not processing lines, which means we're getting raw system() returns
if(WIFEXITED(status))
@ -156,7 +156,7 @@ struct BugpointPass : public Pass {
string bugpoint_file = "bugpoint-case";
if (suffix.size())
bugpoint_file += stringf(".%.8s", suffix.c_str());
bugpoint_file += stringf(".%.8s", suffix);
bugpoint_file += err ? ".err" : ".log";
std::ifstream f(bugpoint_file);
@ -469,13 +469,13 @@ struct BugpointPass : public Pass {
if (args[argidx] == "-script" && argidx + 1 < args.size()) {
if (!yosys_arg.empty())
log_cmd_error("A -script or -command option can be only provided once!\n");
yosys_arg = stringf("-s %s", args[++argidx].c_str());
yosys_arg = stringf("-s %s", args[++argidx]);
continue;
}
if (args[argidx] == "-command" && argidx + 1 < args.size()) {
if (!yosys_arg.empty())
log_cmd_error("A -script or -command option can be only provided once!\n");
yosys_arg = stringf("-p %s", args[++argidx].c_str());
yosys_arg = stringf("-p %s", args[++argidx]);
continue;
}
if (args[argidx] == "-grep" && argidx + 1 < args.size()) {

12
passes/cmds/check.cc
View file

@ -322,7 +322,7 @@ struct CheckPass : public Pass {
if (wire_drivers.count(state)) {
string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state));
for (auto str : wire_drivers[state])
message += stringf(" %s\n", str.c_str());
message += stringf(" %s\n", str);
log_warning("%s", message.c_str());
counter++;
}
@ -331,7 +331,7 @@ struct CheckPass : public Pass {
if (wire_drivers_count[it.first] > 1) {
string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
for (auto str : it.second)
message += stringf(" %s\n", str.c_str());
message += stringf(" %s\n", str);
log_warning("%s", message.c_str());
counter++;
}
@ -394,10 +394,10 @@ struct CheckPass : public Pass {
std::string driver_src;
if (driver->has_attribute(ID::src)) {
std::string src_attr = driver->get_src_attribute();
driver_src = stringf(" source: %s", src_attr.c_str());
driver_src = stringf(" source: %s", src_attr);
}
message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str());
message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src);
if (!coarsened_cells.count(driver)) {
MatchingEdgePrinter printer(message, sigmap, prev, bit);
@ -411,9 +411,9 @@ struct CheckPass : public Pass {
std::string wire_src;
if (wire->has_attribute(ID::src)) {
std::string src_attr = wire->get_src_attribute();
wire_src = stringf(" source: %s", src_attr.c_str());
wire_src = stringf(" source: %s", src_attr);
}
message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src.c_str());
message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src);
}
prev = bit;

10
passes/cmds/dft_tag.cc
View file

@ -372,7 +372,7 @@ struct DftTagWorker {
void propagate_tags(Cell *cell)
{
if (cell->type == ID($set_tag)) {
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
if (all_tags.insert(tag).second) {
auto group_sep = tag.str().find(':');
IdString tag_group = group_sep != std::string::npos ? tag.str().substr(0, group_sep) : tag;
@ -478,7 +478,7 @@ struct DftTagWorker {
void process_cell(IdString tag, Cell *cell)
{
if (cell->type == ID($set_tag)) {
IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
auto &sig_y = cell->getPort(ID::Y);
@ -752,7 +752,7 @@ struct DftTagWorker {
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
tag_signal(tag, sig_a);
}
@ -772,7 +772,7 @@ struct DftTagWorker {
continue;
int index = 0;
auto name = module->uniquify(stringf("%s:%s", wire->name.c_str(), tag.c_str() + 1), index);
auto name = module->uniquify(stringf("%s:%s", wire->name, tag.c_str() + 1), index);
auto hdlname = wire->get_hdlname_attribute();
if (!hdlname.empty())
@ -817,7 +817,7 @@ struct DftTagWorker {
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig = tag_signal(tag, sig_a);
module->connect(sig_y, tag_sig);

10
passes/cmds/glift.cc
View file

@ -163,7 +163,7 @@ private:
std::vector<RTLIL::SigSpec> next_pmux_y_ports, pmux_y_ports(costs.begin(), costs.begin() + exp2(select_width));
for (auto i = 0; pmux_y_ports.size() > 1; ++i) {
for (auto j = 0; j+1 < GetSize(pmux_y_ports); j += 2) {
next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name.c_str(), i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->get_src_attribute()));
next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name, i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->get_src_attribute()));
}
if (GetSize(pmux_y_ports) % 2 == 1)
next_pmux_y_ports.push_back(pmux_y_ports[GetSize(pmux_y_ports) - 1]);
@ -206,7 +206,7 @@ private:
int num_versions = opt_instrumentmore? 8 : 4;
for (auto i = 1; i <= num_versions; ++i)
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name.c_str(), i), 1)));
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1)));
for (auto i = 0; i < num_versions; ++i) {
switch(i) {
@ -239,7 +239,7 @@ private:
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) {
for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) {
next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name.c_str(), i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
}
if (GetSize(meta_mux_y_ports) % 2 == 1)
next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]);
@ -271,7 +271,7 @@ private:
log_assert(exp2(select_width) == num_versions);
for (auto i = 1; i <= num_versions; ++i)
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name.c_str(), i), 1)));
taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1)));
for (auto i = 0; i < num_versions; ++i) {
switch(i) {
@ -294,7 +294,7 @@ private:
std::vector<RTLIL::SigSpec> next_meta_mux_y_ports, meta_mux_y_ports(taint_version);
for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) {
for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) {
next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name.c_str(), i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i]));
}
if (GetSize(meta_mux_y_ports) % 2 == 1)
next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]);

2
passes/cmds/portarcs.cc
View file

@ -243,7 +243,7 @@ struct PortarcsPass : Pass {
if (draw_mode) {
auto bit_str = [](SigBit bit) {
return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()).c_str(), bit.offset);
return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset);
};
std::vector<std::string> headings;

8
passes/cmds/rename.cc
View file

@ -64,7 +64,7 @@ static std::string derive_name_from_src(const std::string &src, int counter)
if (src_base.empty())
return stringf("$%d", counter);
else
return stringf("\\%s$%d", src_base.c_str(), counter);
return stringf("\\%s$%d", src_base, counter);
}
static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, string suffix, bool move_to_cell)
@ -422,7 +422,7 @@ struct RenamePass : public Pass {
if (wire_suffix.empty()) {
for (auto const &[port, _] : cell->connections()) {
if (cell->output(port)) {
wire_suffix += stringf("%s.%s", cell->type.c_str(), port.c_str() + 1);
wire_suffix += stringf("%s.%s", cell->type, port.c_str() + 1);
break;
}
}
@ -449,7 +449,7 @@ struct RenamePass : public Pass {
for (auto wire : module->selected_wires())
if (wire->name[0] == '$') {
RTLIL::IdString buf;
do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix);
while (module->wire(buf) != nullptr);
new_wire_names[wire] = buf;
}
@ -457,7 +457,7 @@ struct RenamePass : public Pass {
for (auto cell : module->selected_cells())
if (cell->name[0] == '$') {
RTLIL::IdString buf;
do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix);
while (module->cell(buf) != nullptr);
new_cell_names[cell] = buf;
}

30
passes/cmds/show.cc
View file

@ -149,7 +149,7 @@ struct ShowWorker
{
for (auto &s : color_selections)
if (s.second.selected_member(module->name, member_name)) {
return stringf("color=\"%s\", fontcolor=\"%s\"", s.first.c_str(), s.first.c_str());
return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first);
}
RTLIL::Const colorattr_value;
@ -308,11 +308,11 @@ struct ShowWorker
std::string repinfo = rep > 1 ? stringf("%dx ", rep) : "";
std::string portside = stringf("%d:%d", bitpos, bitpos - rep*c.width + 1);
std::string remoteside = stringf("%s%d:%d", repinfo.c_str(), cl, cr);
std::string remoteside = stringf("%s%d:%d", repinfo, cl, cr);
if (driver) {
log_assert(!net.empty());
label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, portside.c_str(), remoteside.c_str()));
label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, portside, remoteside));
net_conn_map[net].in.insert({stringf("x%d:s%d", dot_idx, chunk_idx), rep*c.width});
net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
} else {
@ -325,7 +325,7 @@ struct ShowWorker
c.data.front() == State::Sz ? 'Z' : '?',
bitpos, bitpos-rep*c.width+1));
} else {
label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, remoteside.c_str(), portside.c_str()));
label_pieces.push_back(stringf("<s%d> %s - %s ", chunk_idx, remoteside, portside));
net_conn_map[net].out.insert({stringf("x%d:s%d", dot_idx, chunk_idx), rep*c.width});
net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
}
@ -335,14 +335,14 @@ struct ShowWorker
}
code += stringf("x%d [ shape=record, style=rounded, label=\"", dot_idx) \
+ join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig).c_str());
+ join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig));
if (!port.empty()) {
currentColor = xorshift32(currentColor);
if (driver)
code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), dot_idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port, dot_idx, nextColor(sig), widthLabel(sig.size()));
else
code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", dot_idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", dot_idx, port, nextColor(sig), widthLabel(sig.size()));
}
if (node != nullptr)
*node = stringf("x%d", dot_idx);
@ -490,7 +490,7 @@ struct ShowWorker
std::string in_label = join_label_pieces(in_label_pieces);
std::string out_label = join_label_pieces(out_label_pieces);
std::string label_string = stringf("{{%s}|%s\\n%s|{%s}}", in_label.c_str(),
std::string label_string = stringf("{{%s}|%s\\n%s|{%s}}", in_label,
findLabel(cell->name.str()), escape(cell->type.str()),
out_label.c_str());
@ -904,8 +904,8 @@ struct ShowPass : public Pass {
if (libs.size() > 0)
log_header(design, "Continuing show pass.\n");
std::string dot_file = stringf("%s.dot", prefix.c_str());
std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());
std::string dot_file = stringf("%s.dot", prefix);
std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
log("Writing dot description to `%s'.\n", dot_file.c_str());
FILE *f = fopen(dot_file.c_str(), "w");
@ -932,7 +932,7 @@ struct ShowPass : public Pass {
#else
#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
#endif
std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
#if !defined(YOSYS_DISABLE_SPAWN)
@ -950,9 +950,9 @@ struct ShowPass : public Pass {
// system()/cmd.exe does not understand single quotes nor
// background tasks on Windows. So we have to pause yosys
// until the viewer exits.
std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str());
std::string cmd = stringf("%s \"%s\"", viewer_exe, out_file);
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str());
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
@ -960,9 +960,9 @@ struct ShowPass : public Pass {
} else
if (format.empty()) {
#ifdef __APPLE__
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file, dot_file, background);
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)

10
passes/cmds/stat.cc
View file

@ -193,19 +193,19 @@ struct statdata_t {
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
} else if (cell_type.in(ID($mux)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y)));
else if (cell_type.in(ID($bmux), ID($pmux)))
cell_type =
stringf("%s_%d_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
else if (cell_type == ID($demux))
cell_type =
stringf("%s_%d_%d", cell_type.c_str(), GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q)));
}
if (!cell_area.empty()) {

4
passes/cmds/timeest.cc
View file

@ -320,7 +320,7 @@ struct EstimateSta {
std::string cell_src;
if (cell->has_attribute(ID::src)) {
std::string src_attr = cell->get_src_attribute();
cell_src = stringf(" source: %s", src_attr.c_str());
cell_src = stringf(" source: %s", src_attr);
}
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str());
printed.insert(cell);
@ -331,7 +331,7 @@ struct EstimateSta {
std::string wire_src;
if (bit.wire && bit.wire->has_attribute(ID::src)) {
std::string src_attr = bit.wire->get_src_attribute();
wire_src = stringf(" source: %s", src_attr.c_str());
wire_src = stringf(" source: %s", src_attr);
}
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]);
}

14
passes/cmds/viz.cc
View file

@ -982,8 +982,8 @@ struct VizPass : public Pass {
if (modlist.empty())
log_cmd_error("Nothing there to show.\n");
std::string dot_file = stringf("%s.dot", prefix.c_str());
std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str());
std::string dot_file = stringf("%s.dot", prefix);
std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
if (custom_prefix)
yosys_output_files.insert(dot_file);
@ -1026,7 +1026,7 @@ struct VizPass : public Pass {
#else
#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
#endif
std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
#if !defined(YOSYS_DISABLE_SPAWN)
@ -1043,9 +1043,9 @@ struct VizPass : public Pass {
// system()/cmd.exe does not understand single quotes nor
// background tasks on Windows. So we have to pause yosys
// until the viewer exits.
std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str());
std::string cmd = stringf("%s \"%s\"", viewer_exe, out_file);
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str());
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
@ -1053,9 +1053,9 @@ struct VizPass : public Pass {
} else
if (format.empty()) {
#ifdef __APPLE__
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file, dot_file, background);
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str());
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)

4
passes/cmds/wrapcell.cc
View file

@ -97,9 +97,9 @@ struct Chunk {
if (len == cell->getPort(port).size())
return port;
else if (len == 1)
return stringf("%s[%d]", port.c_str(), base);
return stringf("%s[%d]", port, base);
else
return stringf("%s[%d:%d]", port.c_str(), base + len - 1, base);
return stringf("%s[%d:%d]", port, base + len - 1, base);
}
SigSpec sample(Cell *cell)

8
passes/cmds/xprop.cc
View file

@ -978,8 +978,8 @@ struct XpropWorker
if (wire->port_input == wire->port_output) {
log_warning("Port %s not an input or an output port which is not supported by xprop\n", log_id(wire));
} else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) {
auto port_d = module->uniquify(stringf("%s_d", port.c_str()));
auto port_x = module->uniquify(stringf("%s_x", port.c_str()));
auto port_d = module->uniquify(stringf("%s_d", port));
auto port_x = module->uniquify(stringf("%s_x", port));
auto wire_d = module->addWire(port_d, GetSize(wire));
auto wire_x = module->addWire(port_x, GetSize(wire));
@ -1031,8 +1031,8 @@ struct XpropWorker
continue;
int index_d = 0;
int index_x = 0;
auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()), index_d);
auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()), index_x);
auto name_d = module->uniquify(stringf("%s_d", wire->name), index_d);
auto name_x = module->uniquify(stringf("%s_x", wire->name), index_x);
auto hdlname = wire->get_hdlname_attribute();

4
passes/fsm/fsm_extract.cc
View file

@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell
RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm));
RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name, autoidx++), ID($fsm));
fsm_cell->setPort(ID::CLK, clk);
fsm_cell->setPort(ID::ARST, arst);
fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
@ -390,7 +390,7 @@ static void extract_fsm(RTLIL::Wire *wire)
module->wires_.erase(wire->name);
wire->attributes.erase(ID::fsm_encoding);
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
wire->name = stringf("$fsm$oldstate%s", wire->name);
module->wires_[wire->name] = wire;
if(wire->attributes.count(ID::hdlname)) {
auto hdlname = wire->get_hdlname_attribute();

4
passes/hierarchy/flatten.cc
View file

@ -281,11 +281,11 @@ struct FlattenWorker
if (attr.first == ID::hdlname)
scopeinfo->attributes.insert(attr);
else
scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second);
scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second);
}
for (auto const &attr : tpl->attributes)
scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second);
scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first)), attr.second);
scopeinfo->attributes.emplace(ID(module), RTLIL::unescape_id(tpl->name));
}

2
passes/hierarchy/submod.cc
View file

@ -166,7 +166,7 @@ struct SubmodWorker
}
}
else if (hidden_mode)
new_wire_name = stringf("$submod%s", new_wire_name.c_str());
new_wire_name = stringf("$submod%s", new_wire_name);
}
RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);

2
passes/memory/memory_bram.cc
View file

@ -873,7 +873,7 @@ grow_read_ports:;
for (int grid_a = 0; grid_a < acells; grid_a++)
for (int dupidx = 0; dupidx < dup_count; dupidx++)
{
Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid.c_str(), grid_d, grid_a, dupidx)), bram.name);
Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid, grid_d, grid_a, dupidx)), bram.name);
log(" Creating %s cell at grid position <%d %d %d>: %s\n", log_id(bram.name), grid_d, grid_a, dupidx, log_id(c));
for (auto &vp : variant_params)

18
passes/memory/memory_libmap.cc
View file

@ -1686,7 +1686,7 @@ std::vector<SigSpec> generate_mux(Mem &mem, int rpidx, const Swizzle &swz) {
void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, const PortVariant &pdef, const char *name, int wpidx, int rpidx, const std::vector<int> &hw_addr_swizzle) {
for (auto &it: pdef.options)
for (auto cell: cells)
cell->setParam(stringf("\\PORT_%s_OPTION_%s", name, it.first.c_str()), it.second);
cell->setParam(stringf("\\PORT_%s_OPTION_%s", name, it.first), it.second);
SigSpec addr = Const(State::Sx, cfg.def->abits);
int wide_log2 = 0, wr_wide_log2 = 0, rd_wide_log2 = 0;
SigSpec clk = State::S0;
@ -2067,7 +2067,7 @@ void MemMapping::emit(const MemConfig &cfg) {
for (int rp = 0; rp < cfg.repl_port; rp++) {
std::vector<Cell *> cells;
for (int rd = 0; rd < cfg.repl_d; rd++) {
Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid.c_str(), rp, rd), cfg.def->id);
Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid, rp, rd), cfg.def->id);
if (cfg.def->width_mode == WidthMode::Global)
cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]);
if (cfg.def->widthscale) {
@ -2077,18 +2077,18 @@ void MemMapping::emit(const MemConfig &cfg) {
cell->setParam(ID::BITS_USED, val);
}
for (auto &it: cfg.def->options)
cell->setParam(stringf("\\OPTION_%s", it.first.c_str()), it.second);
cell->setParam(stringf("\\OPTION_%s", it.first), it.second);
for (int i = 0; i < GetSize(cfg.def->shared_clocks); i++) {
auto &cdef = cfg.def->shared_clocks[i];
auto &ccfg = cfg.shared_clocks[i];
if (cdef.anyedge) {
cell->setParam(stringf("\\CLK_%s_POL", cdef.name.c_str()), ccfg.used ? ccfg.polarity : true);
cell->setPort(stringf("\\CLK_%s", cdef.name.c_str()), ccfg.used ? ccfg.clk : State::S0);
cell->setParam(stringf("\\CLK_%s_POL", cdef.name), ccfg.used ? ccfg.polarity : true);
cell->setPort(stringf("\\CLK_%s", cdef.name), ccfg.used ? ccfg.clk : State::S0);
} else {
SigSpec sig = ccfg.used ? ccfg.clk : State::S0;
if (ccfg.used && ccfg.invert)
sig = mem.module->Not(NEW_ID, sig);
cell->setPort(stringf("\\CLK_%s", cdef.name.c_str()), sig);
cell->setPort(stringf("\\CLK_%s", cdef.name), sig);
}
}
if (cfg.def->init == MemoryInitKind::Any || cfg.def->init == MemoryInitKind::NoUndef) {
@ -2136,11 +2136,11 @@ void MemMapping::emit(const MemConfig &cfg) {
}
if (pg.optional)
for (auto cell: cells)
cell->setParam(stringf("\\PORT_%s_USED", pg.names[pi].c_str()), used);
cell->setParam(stringf("\\PORT_%s_USED", pg.names[pi]), used);
if (pg.optional_rw)
for (auto cell: cells) {
cell->setParam(stringf("\\PORT_%s_RD_USED", pg.names[pi].c_str()), used_r);
cell->setParam(stringf("\\PORT_%s_WR_USED", pg.names[pi].c_str()), used_w);
cell->setParam(stringf("\\PORT_%s_RD_USED", pg.names[pi]), used_r);
cell->setParam(stringf("\\PORT_%s_WR_USED", pg.names[pi]), used_w);
}
}
}

2
passes/memory/memory_map.cc
View file

@ -244,7 +244,7 @@ struct MemoryMapWorker
data_reg_in[idx] = w_in;
c->setPort(ID::D, w_in);
std::string w_out_name = stringf("%s[%d]", mem.memid.c_str(), addr);
std::string w_out_name = stringf("%s[%d]", mem.memid, addr);
if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(mem.memid, "", addr, "$q");

4
passes/opt/opt_expr.cc
View file

@ -2201,7 +2201,7 @@ skip_alu_split:
{
if (cmp_type == ID($lt)) cmp_name = "<";
if (cmp_type == ID($le)) cmp_name = "<=";
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig));
replacement = "constant 1";
replace_sig[0] = State::S1;
replace = true;
@ -2210,7 +2210,7 @@ skip_alu_split:
{
if (cmp_type == ID($gt)) cmp_name = ">";
if (cmp_type == ID($ge)) cmp_name = ">=";
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig));
replacement = "constant 0";
replace_sig[0] = State::S0;
replace = true;

2
passes/proc/proc_mux.cc
View file

@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
else
{
// create compare cell
RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
apply_attrs(eq_cell, sw, cs);
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);

6
passes/sat/clk2fflogic.cc
View file

@ -72,7 +72,7 @@ struct Clk2fflogicPass : public Pass {
}
std::string sig_str = log_signal(sig);
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig));
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig));
if (is_fine)
module->addFfGate(NEW_ID, sig, sampled_sig);
@ -84,7 +84,7 @@ struct Clk2fflogicPass : public Pass {
SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) {
std::string sig_str = log_signal(sig);
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig));
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig));
if (is_fine)
module->addFfGate(NEW_ID, sig, sampled_sig);
@ -98,7 +98,7 @@ struct Clk2fflogicPass : public Pass {
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig));
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = init;
Cell *cell;

2
passes/sat/cutpoint.cc
View file

@ -129,7 +129,7 @@ struct CutpointPass : public Pass {
if (attr.first == ID::hdlname)
scopeinfo->attributes.insert(attr);
else
scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second);
scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second);
}
}

2
passes/sat/eval.cc
View file

@ -263,7 +263,7 @@ struct VlogHammerReporter
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
}
}

2
passes/sat/fmcombine.cc
View file

@ -44,7 +44,7 @@ struct FmcombineWorker
FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
opts(opts), design(design), original(design->module(orig_type)),
orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type.c_str()))
orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type))
{
}

4
passes/sat/freduce.cc
View file

@ -595,9 +595,9 @@ struct FreduceWorker
void dump()
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter);
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter);
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str());
Pass::call(design, stringf("dump -outfile %s %s", filename.c_str(), design->selected_active_module.empty() ? module->name.c_str() : ""));
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : ""));
}
int run()

4
passes/sat/mutate.cc
View file

@ -570,7 +570,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
string str = "mutate";
if (!opts.ctrl_name.empty())
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += stringf(" -mode %s", entry.mode.c_str());
str += stringf(" -mode %s", entry.mode);
if (!entry.module.empty())
str += stringf(" -module %s", log_id(entry.module));
if (!entry.cell.empty())
@ -586,7 +586,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (entry.wirebit >= 0)
str += stringf(" -wirebit %d", entry.wirebit);
for (auto &s : entry.src)
str += stringf(" -src %s", s.c_str());
str += stringf(" -src %s", s);
if (filename.empty())
log("%s\n", str.c_str());
else

6
passes/sat/qbfsat.cc
View file

@ -219,14 +219,14 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
const std::string smtbmc_warning = "z3: WARNING:";
const std::string smtbmc_cmd = stringf("\"%s\" -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(),
(opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(),
(opt.timeout != 0? stringf("--timeout %d", opt.timeout) : ""),
(opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(),
tempdir_name.c_str(), iter_num);
std::string smt2_command = "write_smt2 -stbv -wires ";
for (auto &solver_opt : opt.solver_options)
smt2_command += stringf("-solver-option %s %s ", solver_opt.first.c_str(), solver_opt.second.c_str());
smt2_command += stringf("%s/problem%d.smt2", tempdir_name.c_str(), iter_num);
smt2_command += stringf("-solver-option %s %s ", solver_opt.first, solver_opt.second);
smt2_command += stringf("%s/problem%d.smt2", tempdir_name, iter_num);
Pass::call(mod->design, smt2_command);
auto process_line = [&ret, &smtbmc_warning, &opt, &quiet](const std::string &line) {

4
passes/sat/recover_names.cc
View file

@ -380,7 +380,7 @@ struct RecoverModuleWorker {
if (root2buffered.count(gate_bit)) {
int buf_idx = 0;
for (auto buf_bit : root2buffered.at(gate_bit)) {
std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name.c_str(), ++buf_idx);
std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name, ++buf_idx);
if (buf_name_str[0] == '\\')
buf_name_str[0] = '$';
rename_map[buf_bit] = std::make_pair(
@ -396,7 +396,7 @@ struct RecoverModuleWorker {
bool must_invert_name = rule.second.first.inverted;
while (must_invert_name ||
(mod->wire(new_name.name) && !unused_bits.count(SigBit(mod->wire(new_name.name), new_name.bit)))) {
std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name.c_str(),
std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name,
rule.second.first.inverted ? "inv" : "dup", ++dup_idx);
if (new_name_str[0] == '\\')
new_name_str[0] = '$';

50
passes/sat/sim.cc
View file

@ -2095,12 +2095,12 @@ struct SimWorker : SimShared
std::stringstream f;
if (wire->width==1)
f << stringf("%s", RTLIL::unescape_id(wire->name).c_str());
f << stringf("%s", RTLIL::unescape_id(wire->name));
else
if (wire->upto)
f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name).c_str());
f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name));
else
f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name).c_str());
f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name));
return f.str();
}
@ -2108,7 +2108,7 @@ struct SimWorker : SimShared
{
std::stringstream f;
for(auto item=signals.begin();item!=signals.end();item++)
f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str());
f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name));
return f.str();
}
@ -2207,7 +2207,7 @@ struct SimWorker : SimShared
std::stringstream f;
f << stringf("`timescale 1%s/1%s\n", fst->getTimescaleString(),fst->getTimescaleString());
f << stringf("module %s();\n",tb_filename.c_str());
f << stringf("module %s();\n",tb_filename);
int clk_len = 0;
int inputs_len = 0;
int outputs_len = 0;
@ -2225,13 +2225,13 @@ struct SimWorker : SimShared
}
int data_len = clk_len + inputs_len + outputs_len + 32;
f << "\n";
f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name).c_str());
f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name));
for(auto item=clocks.begin();item!=clocks.end();item++)
f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str(), RTLIL::unescape_id(item->first->name).c_str());
f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name), RTLIL::unescape_id(item->first->name));
for(auto &item : inputs)
f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str());
f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name));
for(auto &item : outputs)
f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str());
f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name));
f << ");\n";
f << "\n";
f << "\tinteger i;\n";
@ -2242,21 +2242,21 @@ struct SimWorker : SimShared
unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX;
fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, end_cycle, [&](uint64_t time) {
for(auto &item : clocks)
data_file << stringf("%s",fst->valueOf(item.second).c_str());
data_file << stringf("%s",fst->valueOf(item.second));
for(auto &item : inputs)
data_file << stringf("%s",fst->valueOf(item.second).c_str());
data_file << stringf("%s",fst->valueOf(item.second));
for(auto &item : outputs)
data_file << stringf("%s",fst->valueOf(item.second).c_str());
data_file << stringf("%s\n",Const(time-prev_time).as_string().c_str());
data_file << stringf("%s",fst->valueOf(item.second));
data_file << stringf("%s\n",Const(time-prev_time).as_string());
if (time==startCount) {
// initial state
for(auto var : fst->getVars()) {
if (var.is_reg && !Const::from_string(fst->valueOf(var.id).c_str()).is_fully_undef()) {
if (var.scope == scope) {
initstate << stringf("\t\tuut.%s = %d'b%s;\n", var.name.c_str(), var.width, fst->valueOf(var.id).c_str());
initstate << stringf("\t\tuut.%s = %d'b%s;\n", var.name, var.width, fst->valueOf(var.id));
} else if (var.scope.find(scope+".")==0) {
initstate << stringf("\t\tuut.%s.%s = %d'b%s;\n",var.scope.substr(scope.size()+1).c_str(), var.name.c_str(), var.width, fst->valueOf(var.id).c_str());
initstate << stringf("\t\tuut.%s.%s = %d'b%s;\n",var.scope.substr(scope.size()+1), var.name, var.width, fst->valueOf(var.id));
}
}
}
@ -2267,22 +2267,22 @@ struct SimWorker : SimShared
f << stringf("\treg [0:%d] data [0:%d];\n", data_len-1, cycle-1);
f << "\tinitial begin;\n";
f << stringf("\t\t$dumpfile(\"%s\");\n",tb_filename.c_str());
f << stringf("\t\t$dumpvars(0,%s);\n",tb_filename.c_str());
f << stringf("\t\t$dumpfile(\"%s\");\n",tb_filename);
f << stringf("\t\t$dumpvars(0,%s);\n",tb_filename);
f << initstate.str();
f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename.c_str());
f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename);
f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1);
f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1);
f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1);
f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle);
f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1);
f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1);
f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1);
f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs).c_str(), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1);
f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1);
f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n";
f << "\t\t\tend\n";
@ -2337,7 +2337,7 @@ struct VCDWriter : public OutputWriter
}
if (!worker->timescale.empty())
vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str());
vcdfile << stringf("$timescale %s $end\n", worker->timescale);
worker->top->write_output_header(
[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
@ -2349,7 +2349,7 @@ struct VCDWriter : public OutputWriter
// this is consistent with the range gtkwave makes up if it doesn't find a
// range
std::string full_name = form_vcd_name(name, size, w);
vcdfile << stringf("$var %s %d n%d %s%s $end\n", is_reg ? "reg" : "wire", size, id, name[0] == '$' ? "\\" : "", full_name.c_str());
vcdfile << stringf("$var %s %d n%d %s%s $end\n", is_reg ? "reg" : "wire", size, id, name[0] == '$' ? "\\" : "", full_name);
}
);

38
passes/techmap/abc.cc
View file

@ -859,27 +859,27 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, config.show_tempdir).c_str());
std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str());
std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name);
if (!config.liberty_files.empty() || !config.genlib_files.empty()) {
std::string dont_use_args;
for (std::string dont_use_cell : config.dont_use_cells) {
dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str());
dont_use_args += stringf("-X \"%s\" ", dont_use_cell);
}
bool first_lib = true;
for (std::string liberty_file : config.liberty_files) {
abc_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args.c_str(), first_lib ? "" : "-m", liberty_file.c_str());
abc_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args, first_lib ? "" : "-m", liberty_file);
first_lib = false;
}
for (std::string liberty_file : config.genlib_files)
abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str());
abc_script += stringf("read_library \"%s\"; ", liberty_file);
if (!config.constr_file.empty())
abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file.c_str());
abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file);
} else
if (!config.lut_costs.empty())
abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name);
else
abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name);
if (!config.script_file.empty()) {
const std::string &script_file = config.script_file;
@ -892,7 +892,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
else
abc_script += script_file[i];
} else
abc_script += stringf("source %s", script_file.c_str());
abc_script += stringf("source %s", script_file);
} else if (!config.lut_costs.empty()) {
bool all_luts_cost_same = true;
for (int this_cost : config.lut_costs)
@ -925,15 +925,15 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3);
if (config.abc_dress)
abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name.c_str());
abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name);
abc_script += stringf("; write_blif %s/output.blif", tempdir_name);
abc_script = add_echos_to_abc_cmd(abc_script);
for (size_t i = 0; i+1 < abc_script.size(); i++)
if (abc_script[i] == ';' && abc_script[i+1] == ' ')
abc_script[i+1] = '\n';
std::string buffer = stringf("%s/abc.script", tempdir_name.c_str());
std::string buffer = stringf("%s/abc.script", tempdir_name);
FILE *f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
@ -988,7 +988,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
handle_loops(assign_map, module);
buffer = stringf("%s/input.blif", tempdir_name.c_str());
buffer = stringf("%s/input.blif", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
@ -1115,7 +1115,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
buffer = stringf("%s/stdcells.genlib", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
@ -1160,7 +1160,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
fclose(f);
if (!config.lut_costs.empty()) {
buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
buffer = stringf("%s/lutdefs.txt", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
@ -1169,14 +1169,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
fclose(f);
}
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str());
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str());
#ifndef YOSYS_LINK_ABC
abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
#else
string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str());
string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name);
FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w");
if (temp_stdouterr_w == NULL)
log_error("ABC: cannot open a temporary file for output redirection");
@ -1196,7 +1196,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
fclose(temp_stdouterr_w);
// These needs to be mutable, supposedly due to getopt
char *abc_argv[5];
string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
string tmp_script_name = stringf("%s/abc.script", tempdir_name);
abc_argv[0] = strdup(config.exe_file.c_str());
abc_argv[1] = strdup("-s");
abc_argv[2] = strdup("-f");
@ -1235,7 +1235,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
return;
}
std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
std::string buffer = stringf("%s/%s", tempdir_name, "output.blif");
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
@ -2102,7 +2102,7 @@ struct AbcPass : public Pass {
goto ok_alias;
}
if (g_arg_from_cmd)
cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str()));
cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g));
else
log_cmd_error("Unsupported gate type: %s", g.c_str());
ok_gate:

20
passes/techmap/abc9.cc
View file

@ -332,8 +332,8 @@ struct Abc9Pass : public ScriptPass
// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
for (auto module : active_design->selected_modules()) {
active_design->selected_active_module = module->name.str();
if (module->cell(stringf("%s_$abc9_flop", module->name.c_str())))
run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
if (module->cell(stringf("%s_$abc9_flop", module->name)))
run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name));
}
active_design->selected_active_module.clear();
}
@ -418,10 +418,10 @@ struct Abc9Pass : public ScriptPass
tempdir_name = make_temp_dir(tempdir_name);
if (!lut_mode)
run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name));
if (box_file.empty())
run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
run_nocheck(stringf("write_xaiger -map %s/input.sym %s %s/input.xaig", tempdir_name.c_str(), dff_mode ? "-dff" : "", tempdir_name.c_str()));
run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name));
run_nocheck(stringf("write_xaiger -map %s/input.sym %s %s/input.xaig", tempdir_name, dff_mode ? "-dff" : "", tempdir_name));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
@ -433,15 +433,15 @@ struct Abc9Pass : public ScriptPass
num_outputs);
if (num_outputs) {
std::string abc9_exe_cmd;
abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str());
abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str(), tempdir_name);
if (!lut_mode)
abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name);
if (box_file.empty())
abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name);
else
abc9_exe_cmd += stringf(" -box %s", box_file.c_str());
abc9_exe_cmd += stringf(" -box %s", box_file);
run_nocheck(abc9_exe_cmd);
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name, tempdir_name));
run_nocheck(stringf("abc9_ops -reintegrate %s", dff_mode ? "-dff" : ""));
}
else

32
passes/techmap/abc9_exe.cc
View file

@ -173,28 +173,28 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
std::string abc9_script;
if (!lut_costs.empty())
abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name);
else if (!lut_file.empty())
abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str());
abc9_script += stringf("read_lut \"%s\"; ", lut_file);
else if (!liberty_files.empty()) {
std::string dont_use_args;
for (std::string dont_use_cell : dont_use_cells) {
dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str());
dont_use_args += stringf("-X \"%s\" ", dont_use_cell);
}
for (std::string liberty_file : liberty_files) {
abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str());
abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args, liberty_file);
}
if (!constr_file.empty())
abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str());
abc9_script += stringf("read_constr -v \"%s\"; ", constr_file);
} else if (!genlib_files.empty()) {
for (std::string genlib_file : genlib_files) {
abc9_script += stringf("read_genlib \"%s\"; ", genlib_file.c_str());
abc9_script += stringf("read_genlib \"%s\"; ", genlib_file);
}
}
log_assert(!box_file.empty());
abc9_script += stringf("read_box \"%s\"; ", box_file.c_str());
abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
abc9_script += stringf("read_box \"%s\"; ", box_file);
abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name);
if (!script_file.empty()) {
if (script_file[0] == '+') {
@ -206,7 +206,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
else
abc9_script += script_file[i];
} else
abc9_script += stringf("source %s", script_file.c_str());
abc9_script += stringf("source %s", script_file);
} else if (!lut_costs.empty() || !lut_file.empty()) {
abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)
: RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos);
@ -238,14 +238,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
abc9_script = abc9_script.erase(pos, strlen("&mfs"));
else {
auto s = stringf("&write -n %s/output.aig; ", tempdir_name.c_str());
auto s = stringf("&write -n %s/output.aig; ", tempdir_name);
for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos)) {
abc9_script = abc9_script.insert(pos, s);
pos += GetSize(s) + strlen("&mfs");
}
}
abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name.c_str());
abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name);
if (design->scratchpad_get_bool("abc9.verify")) {
if (dff_mode)
abc9_script += "; &verify -s";
@ -268,7 +268,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
log_header(design, "Executing ABC9.\n");
if (!lut_costs.empty()) {
buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
buffer = stringf("%s/lutdefs.txt", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == NULL)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
@ -277,14 +277,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
fclose(f);
}
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file, tempdir_name);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
#ifndef YOSYS_LINK_ABC
abc9_output_filter filt(tempdir_name, show_tempdir);
int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1));
#else
string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str());
string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name);
FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w");
if (temp_stdouterr_w == NULL)
log_error("ABC: cannot open a temporary file for output redirection");
@ -304,7 +304,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
fclose(temp_stdouterr_w);
// These needs to be mutable, supposedly due to getopt
char *abc9_argv[5];
string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
string tmp_script_name = stringf("%s/abc.script", tempdir_name);
abc9_argv[0] = strdup(exe_file.c_str());
abc9_argv[1] = strdup("-s");
abc9_argv[2] = strdup("-f");
@ -328,7 +328,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
temp_stdouterr_r.close();
#endif
if (ret != 0) {
if (check_file_exists(stringf("%s/output.aig", tempdir_name.c_str())))
if (check_file_exists(stringf("%s/output.aig", tempdir_name)))
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
else
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);

12
passes/techmap/abc9_ops.cc
View file

@ -856,7 +856,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
else if (w->port_output)
conn = holes_module->addWire(stringf("%s.%s", cell->type.c_str(), log_id(port_name)), GetSize(w));
conn = holes_module->addWire(stringf("%s.%s", cell->type, log_id(port_name)), GetSize(w));
}
}
else // box_module is a blackbox
@ -868,7 +868,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(w);
if (!w->port_output)
continue;
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, log_id(port_name)), GetSize(w));
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
@ -1143,7 +1143,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
map_autoidx = autoidx++;
RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name));
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
@ -1271,16 +1271,16 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// (TODO: Optimise by not cloning unless will increase depth)
RTLIL::IdString driver_name;
if (GetSize(a_bit.wire) == 1)
driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
driver_name = stringf("$lut%s", a_bit.wire->name);
else
driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
driver_name = stringf("$lut%s[%d]", a_bit.wire->name, a_bit.offset);
driver_lut = mapped_mod->cell(driver_name);
}
if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name)),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));

6
passes/techmap/abc_new.cc
View file

@ -168,9 +168,9 @@ struct AbcNewPass : public ScriptPass {
mod->get_string_attribute(ID(abc9_script)));
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str()));
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str()));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str()));
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir));
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir));
run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));

2
passes/techmap/booth.cc
View file

@ -201,7 +201,7 @@ struct BoothPassWorker {
log_assert(sig_a.size() == sig_y.size());
for (int i = 0; i < sig_a.size(); i++)
mod->addFa(stringf("%s[%d]", name.c_str(), i), sig_a[i], sig_b[i],
mod->addFa(stringf("%s[%d]", name, i), sig_a[i], sig_b[i],
sig_c[i], sig_x[i], sig_y[i], src);
}

4
passes/techmap/dfflibmap.cc
View file

@ -553,7 +553,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
new_cell->setPort("\\" + port.first, sig);
}
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type, new_cell->type)]++;
}
for (auto &stat: stats)
@ -687,7 +687,7 @@ struct DfflibmapPass : public Pass {
if (!map_only_mode) {
std::string dfflegalize_cmd = "dfflegalize";
for (auto it : cell_mappings)
dfflegalize_cmd += stringf(" -cell %s 01", it.first.c_str());
dfflegalize_cmd += stringf(" -cell %s 01", it.first);
dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
if (info_mode) {
log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str());

2
passes/techmap/extract.cc
View file

@ -292,7 +292,7 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit:
SigSet<std::pair<RTLIL::IdString, int>> sig2port;
// create new cell
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name, autoidx++), needle->name);
// create cell ports
for (auto wire : needle->wires()) {

14
passes/techmap/techmap.cc
View file

@ -42,9 +42,9 @@ PRIVATE_NAMESPACE_BEGIN
void apply_prefix(IdString prefix, IdString &id)
{
if (id[0] == '\\')
id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
id = stringf("%s.%s", prefix, id.c_str()+1);
else
id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
id = stringf("$techmap%s.%s", prefix, id);
}
void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
@ -107,7 +107,7 @@ struct TechmapWorker
}
}
return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
return stringf("$paramod$constmap:%s%s", sha1(constmap_info), tpl->name);
}
TechmapWires techmap_find_special_wires(RTLIL::Module *module)
@ -222,7 +222,7 @@ struct TechmapWorker
design->select(module, w);
if (const char *p = strstr(tpl_w->name.c_str(), "_TECHMAP_REPLACE_.")) {
IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), p + strlen("_TECHMAP_REPLACE_"));
IdString replace_name = stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_"));
Wire *replace_w = module->addWire(replace_name, tpl_w);
module->connect(replace_w, w);
}
@ -327,7 +327,7 @@ struct TechmapWorker
if (techmap_replace_cell)
c_name = orig_cell_name;
else if (const char *p = strstr(tpl_cell->name.c_str(), "_TECHMAP_REPLACE_."))
c_name = stringf("%s%s", orig_cell_name.c_str(), p + strlen("_TECHMAP_REPLACE_"));
c_name = stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_"));
else
apply_prefix(cell->name, c_name);
@ -512,7 +512,7 @@ struct TechmapWorker
if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type));
for (auto &c : cell->parameters)
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
@ -586,7 +586,7 @@ struct TechmapWorker
}
else
{
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());

66
passes/tests/test_autotb.cc
View file

@ -114,7 +114,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
if (wire->port_output) {
count_ports++;
signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()));
} else if (wire->port_input) {
count_ports++;
bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock);
@ -134,73 +134,73 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
if (wire->attributes.count(ID::gentb_constant) != 0)
signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string();
}
f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()));
}
}
f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
f << stringf("%s %s(\n", id(mod->name.str()), idy("uut", mod->name.str()));
for (auto wire : mod->wires()) {
if (wire->port_output || wire->port_input)
f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
f << stringf("\t.%s(%s)%s\n", id(wire->name.str()),
idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
}
f << stringf(");\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "reset"));
f << stringf("begin\n");
int delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d 0;\n", it->first, ++delay_counter*2);
for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it)
f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d 0;\n", it->first, ++delay_counter*2);
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
f << stringf("\t#100; %s <= 1;\n", it->first);
f << stringf("\t#100; %s <= 0;\n", it->first);
}
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d ~0;\n", it->first, ++delay_counter*2);
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
f << stringf("\t#100; %s <= 1;\n", it->first);
f << stringf("\t#100; %s <= 0;\n", it->first);
}
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); ++it) {
if (signal_const.count(it->first) == 0)
continue;
f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str());
f << stringf("\t%s <= #%d 'b%s;\n", it->first, ++delay_counter*2, signal_const[it->first]);
}
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "update_data"));
f << stringf("begin\n");
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
if (signal_const.count(it->first) > 0)
continue;
f << stringf("\txorshift128;\n");
f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first, ++delay_counter*2);
}
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "update_clock"));
f << stringf("begin\n");
if (signal_clk.size()) {
f << stringf("\txorshift128;\n");
f << stringf("\t{");
int total_clock_bits = 0;
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first);
total_clock_bits += it->second;
}
f << stringf(" } = {");
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first);
f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits + 1);
}
f << stringf("end\n");
@ -210,12 +210,12 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
std::vector<std::string> header1;
std::string header2 = "";
f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "print_status"));
f << stringf("begin\n");
f << stringf("\t$fdisplay(file, \"#OUT# %%b %%b %%b %%t %%d\", {");
if (signal_in.size())
for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first);
int len = it->second;
header2 += ", \"";
if (len > 1)
@ -237,7 +237,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
header2 += ", \" \"";
if (signal_clk.size()) {
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first);
int len = it->second;
header2 += ", \"";
if (len > 1)
@ -259,7 +259,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
header2 += ", \" \"";
if (signal_out.size()) {
for (auto it = signal_out.begin(); it != signal_out.end(); it++) {
f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first);
int len = it->second;
header2 += ", \"";
if (len > 1)
@ -281,25 +281,25 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "print_header"));
f << stringf("begin\n");
f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
for (auto &hdr : header1)
f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr.c_str());
f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr);
f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2.c_str());
f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2);
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "test"));
f << stringf("begin\n");
f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str());
f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()));
f << stringf("\t%s;\n", idy(mod->name.str(), "reset"));
f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header"));
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data"));
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock"));
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status"));
f << stringf("\tend\n");
f << stringf("end\n");
f << stringf("endtask\n\n");
@ -317,7 +317,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
f << stringf("\tend\n");
for (auto module : design->modules())
if (!module->get_bool_attribute(ID::gentb_skip))
f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str());
f << stringf("\t%s;\n", idy(module->name.str(), "test"));
f << stringf("\t$fclose(file);\n");
f << stringf("\t$finish;\n");
f << stringf("end\n\n");

26
passes/tests/test_cell.cc
View file

@ -591,7 +591,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
if (vlog_file.is_open())
{
vlog_file << stringf("\nmodule %s;\n", uut_name.c_str());
vlog_file << stringf("\nmodule %s;\n", uut_name);
for (auto port : gold_mod->ports) {
RTLIL::Wire *wire = gold_mod->wire(port);
@ -601,13 +601,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", GetSize(wire)-1, log_id(wire), log_id(wire));
}
vlog_file << stringf(" %s_expr uut_expr(", uut_name.c_str());
vlog_file << stringf(" %s_expr uut_expr(", uut_name);
for (int i = 0; i < GetSize(gold_mod->ports); i++)
vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr");
vlog_file << stringf(");\n");
vlog_file << stringf(" %s_expr uut_noexpr(", uut_name.c_str());
vlog_file << stringf(" %s_expr uut_noexpr(", uut_name);
for (int i = 0; i < GetSize(gold_mod->ports); i++)
vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr");
@ -615,7 +615,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
vlog_file << stringf(" task run;\n");
vlog_file << stringf(" begin\n");
vlog_file << stringf(" $display(\"%s\");\n", uut_name.c_str());
vlog_file << stringf(" $display(\"%s\");\n", uut_name);
}
for (int i = 0; i < 64; i++)
@ -662,7 +662,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
gate_ce.set(gate_wire, in_value);
if (vlog_file.is_open() && GetSize(in_value) > 0) {
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string());
if (!vlog_pattern_info.empty())
vlog_pattern_info += " ";
vlog_pattern_info += stringf("%s=%s", log_id(gold_wire), log_signal(in_value));
@ -716,8 +716,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
if (vlog_file.is_open()) {
vlog_file << stringf(" $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n",
vlog_pattern_info.c_str(), log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string());
vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string());
}
}
@ -1142,12 +1142,12 @@ struct TestCellPass : public Pass {
else
uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) {
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i));
} else if (edges) {
Pass::call(design, "dump gold");
run_edges_test(design, verbose);
} else {
Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd.c_str()));
Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd));
if (!noopt)
Pass::call(design, "opt -fast gate");
if (!nosat)
@ -1157,11 +1157,11 @@ struct TestCellPass : public Pass {
Pass::call(design, "dump gold");
if (!nosat)
Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i);
std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1), i);
if (vlog_file.is_open()) {
Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str()));
Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name, uut_name));
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str()));
Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name, uut_name));
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
uut_names.push_back(uut_name);
}
@ -1208,7 +1208,7 @@ struct TestCellPass : public Pass {
if (vlog_file.is_open()) {
vlog_file << "\nmodule testbench;\n";
for (auto &uut : uut_names)
vlog_file << stringf(" %s %s ();\n", uut.c_str(), uut.c_str());
vlog_file << stringf(" %s %s ();\n", uut, uut);
vlog_file << " initial begin\n";
for (auto &uut : uut_names)
vlog_file << " " << uut << ".run;\n";