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More freduce cleanups

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This commit is contained in:
Clifford Wolf 2014-01-03 18:17:28 +01:00
parent 8f11eaaca6
commit c44e1bec6d
1 changed files with 24 additions and 0 deletions
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24
passes/sat/freduce.cc
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@ -52,6 +52,22 @@ struct equiv_bit_t
} }
}; };
struct CountBitUsage
{
SigMap &sigmap;
std::map<RTLIL::SigBit, int> &cache;
CountBitUsage(SigMap &sigmap, std::map<RTLIL::SigBit, int> &cache) : sigmap(sigmap), cache(cache) { }
void operator()(RTLIL::SigSpec &sig)
{
std::vector<RTLIL::SigBit> vec = sigmap(sig).to_sigbit_vector();
for (auto &bit : vec) {
log("%s %d\n", log_signal(bit), cache[bit]++);
}
}
};
struct FindReducedInputs struct FindReducedInputs
{ {
SigMap &sigmap; SigMap &sigmap;
@ -478,6 +494,9 @@ struct FreduceWorker
worker.analyze(equiv); worker.analyze(equiv);
} }
std::map<RTLIL::SigBit, int> bitusage;
module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage));
log(" Rewiring %d equivialent groups:\n", int(equiv.size())); log(" Rewiring %d equivialent groups:\n", int(equiv.size()));
int rewired_sigbits = 0; int rewired_sigbits = 0;
for (auto &grp : equiv) for (auto &grp : equiv)
@ -492,6 +511,11 @@ struct FreduceWorker
continue; continue;
} }
if (grp[i].bit.wire->port_id == 0 && bitusage[grp[i].bit] <= 1) {
log(" Skipping unused slave: %s\n", log_signal(grp[i].bit));
continue;
}
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Cell *drv = drivers.at(grp[i].bit).first;