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Add equiv_opt -multiclock

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-09-11 13:55:16 +01:00
parent c7f1368cd2
commit c43e52d2d7
2 changed files with 23 additions and 1 deletions
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12
tests/various/equiv_opt_multiclock.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOT
module top(input clk, pre, d, output reg q);
always @(posedge clk, posedge pre)
if (pre)
q <= 1'b1;
else
q <= d;
endmodule
EOT
prep
equiv_opt -assert -multiclock -map +/simcells.v synth