mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00
Code Activity

quicklogic: Fix cascading

Browse source
This commit is contained in:
Martin Povišer 2025-03-10 16:25:02 +01:00
parent 6a3d1cc976
commit c439f8c770
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
techlibs/quicklogic/ql_dsp.pmg
View file

@ -260,6 +260,7 @@ code
dsp2->setParam(\ROUND, Const(0, 3));
dsp2->setParam(\SHIFT_REG, Const(0, 6));
dsp2->setParam(\SATURATE, Const(0, 1));
dsp2->setParam(\ZCIN_REG, Const(1, 1));
dsp2->setPort(\z_o, {port(dsp2, \z_o).extract_end(port(add, \Y).size()), port(add, \Y)});
module->remove(add);