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Fix broken abc9.v test due to inout being 1'bx

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This commit is contained in:
Eddie Hung 2019-06-20 19:27:00 -07:00
parent a0566b03ec
commit c421d48d6d
2 changed files with 21 additions and 5 deletions
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13
frontends/aiger/aigerparse.cc
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@ -836,6 +836,10 @@ void AigerReader::post_process()
RTLIL::Wire* wire = outputs[variable + co_count];
log_assert(wire);
log_assert(wire->port_output);
if (escaped_s == "$__dummy__") {
wire->port_output = false;
continue;
}
if (index == 0) {
// Cope with the fact that a CO might be identical
@ -945,12 +949,15 @@ void AigerReader::post_process()
other_wire->port_input = false;
other_wire->port_output = false;
}
if (wire->port_input && other_wire)
module->connect(other_wire, SigSpec(wire, i));
else
if (wire->port_input) {
if (other_wire)
module->connect(other_wire, SigSpec(wire, i));
}
else {
// Since we skip POs that are connected to Sx,
// re-connect them here
module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
}
}
}