mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-01 13:08:54 +00:00
Merge 5328762fe5 into 5d7486115a
This commit is contained in:
nella
GitHub
commit
c3f0f62039
5 changed files with 480 additions and 15 deletions
156
tests/arch/nexus/pipe_mul.sv
Normal file
156
tests/arch/nexus/pipe_mul.sv
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
// https://github.com/YosysHQ/yosys/issues/5917
|
||||
|
||||
module mul18_pipe(
|
||||
input logic clk,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
logic [17:0] a_r;
|
||||
logic [17:0] b_r;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
a_r <= a;
|
||||
b_r <= b;
|
||||
y <= a_r * b_r;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mul18_pipe_signed (
|
||||
input logic clk,
|
||||
input logic signed [17:0] a,
|
||||
input logic signed [17:0] b,
|
||||
output logic signed [35:0] y
|
||||
);
|
||||
logic signed [17:0] a_r;
|
||||
logic signed [17:0] b_r;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
a_r <= a;
|
||||
b_r <= b;
|
||||
y <= a_r * b_r;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
module mul18_pipe_in_only (
|
||||
input logic clk,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
logic [17:0] a_r;
|
||||
logic [17:0] b_r;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
a_r <= a;
|
||||
b_r <= b;
|
||||
end
|
||||
|
||||
assign y = a_r * b_r;
|
||||
endmodule
|
||||
|
||||
module mul18_pipe_out_only (
|
||||
input logic clk,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
always_ff @(posedge clk)
|
||||
y <= a * b;
|
||||
endmodule
|
||||
|
||||
module mul18_pipe_io_rst (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
logic [17:0] a_r;
|
||||
logic [17:0] b_r;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) begin a_r <= 0; b_r <= 0; y <= 0; end
|
||||
else begin a_r <= a; b_r <= b; y <= a_r * b_r; end
|
||||
endmodule
|
||||
|
||||
module mul24_io (
|
||||
input logic clk,
|
||||
input logic [23:0] a,
|
||||
input logic [23:0] b,
|
||||
output logic [47:0] y
|
||||
);
|
||||
logic [23:0] a_r;
|
||||
logic [23:0] b_r;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
a_r <= a;
|
||||
b_r <= b;
|
||||
y <= a_r * b_r;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mul32_io (
|
||||
input logic clk,
|
||||
input logic [31:0] a,
|
||||
input logic [31:0] b,
|
||||
output logic [63:0] y
|
||||
);
|
||||
logic [31:0] a_r;
|
||||
logic [31:0] b_r;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
a_r <= a;
|
||||
b_r <= b;
|
||||
y <= a_r * b_r;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mul18_negedge (
|
||||
input logic clk,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
logic [17:0] a_r;
|
||||
logic [17:0] b_r;
|
||||
|
||||
always_ff @(negedge clk) begin
|
||||
a_r <= a;
|
||||
b_r <= b;
|
||||
y <= a_r * b_r;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mul18_rst_nonzero (
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
logic [17:0] a_r;
|
||||
logic [17:0] b_r;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (rst) begin a_r <= 18'h3; b_r <= 18'h7; end
|
||||
else begin a_r <= a; b_r <= b; end
|
||||
always_ff @(posedge clk)
|
||||
y <= a_r * b_r;
|
||||
endmodule
|
||||
|
||||
module mul18_two_clock (
|
||||
input logic clk0,
|
||||
input logic clk1,
|
||||
input logic [17:0] a,
|
||||
input logic [17:0] b,
|
||||
output logic [35:0] y
|
||||
);
|
||||
logic [17:0] a_r;
|
||||
logic [17:0] b_r;
|
||||
|
||||
always_ff @(posedge clk0) a_r <= a;
|
||||
always_ff @(posedge clk1) b_r <= b;
|
||||
assign y = a_r * b_r;
|
||||
endmodule
|
||||
74
tests/arch/nexus/pipe_mul.ys
Normal file
74
tests/arch/nexus/pipe_mul.ys
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
read_verilog -sv pipe_mul.sv
|
||||
|
||||
design -save pristine
|
||||
|
||||
# 18x18 MULT
|
||||
design -load pristine
|
||||
hierarchy -top mul18_pipe
|
||||
synth_nexus -family lifcl -top mul18_pipe
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# 18x18 MULT (signed)
|
||||
design -load pristine
|
||||
hierarchy -top mul18_pipe_signed
|
||||
synth_nexus -family lifcl -top mul18_pipe_signed
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# 18x18 MULT (input only)
|
||||
design -load pristine
|
||||
hierarchy -top mul18_pipe_in_only
|
||||
synth_nexus -family lifcl -top mul18_pipe_in_only
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=BYPASS
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# 18x18 MULT (output only)
|
||||
design -load pristine
|
||||
hierarchy -top mul18_pipe_out_only
|
||||
synth_nexus -family lifcl -top mul18_pipe_out_only
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS r:REGOUTPUT=REGISTER
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# 18x18 MULT (reset)
|
||||
design -load pristine
|
||||
hierarchy -top mul18_pipe_io_rst
|
||||
synth_nexus -family lifcl -top mul18_pipe_io_rst
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# 24x24 MUL -> pipelined 36X36 MULT
|
||||
design -load pristine
|
||||
hierarchy -top mul24_io
|
||||
synth_nexus -family lifcl -top mul24_io
|
||||
select -assert-count 1 t:MULT36X36 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# 32x32 MUL -> pipelined 36X36 MULT
|
||||
design -load pristine
|
||||
hierarchy -top mul32_io
|
||||
synth_nexus -family lifcl -top mul32_io
|
||||
select -assert-count 1 t:MULT36X36 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
|
||||
select -assert-count 0 t:FD1P3*
|
||||
|
||||
# reject
|
||||
# DSP reg is rising-edge
|
||||
design -load pristine
|
||||
hierarchy -top mul18_negedge
|
||||
synth_nexus -family lifcl -top mul18_negedge
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS r:REGOUTPUT=BYPASS
|
||||
select -assert-min 1 t:FD1P3*
|
||||
|
||||
# DSP reg only resets to 0
|
||||
design -load pristine
|
||||
hierarchy -top mul18_rst_nonzero
|
||||
synth_nexus -family lifcl -top mul18_rst_nonzero
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS r:REGOUTPUT=BYPASS
|
||||
select -assert-min 1 t:FD1P3*
|
||||
|
||||
# two clocks feeding input regs -> can't share one CLK pin
|
||||
design -load pristine
|
||||
hierarchy -top mul18_two_clock
|
||||
synth_nexus -family lifcl -top mul18_two_clock
|
||||
select -assert-count 1 t:MULT18X18 r:REGINPUTA=BYPASS r:REGINPUTB=BYPASS
|
||||
select -assert-min 1 t:FD1P3*
|
||||
Loading…
Add table
Add a link
Reference in a new issue