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Added $_BUF_ cell type

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This commit is contained in:
Clifford Wolf 2014-10-03 10:12:28 +02:00
parent 600c6cb013
commit c3e779a65f
5 changed files with 19 additions and 5 deletions
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3
kernel/celltypes.h
View file

@ -130,6 +130,7 @@ struct CellTypes
void setup_stdcells() void setup_stdcells()
{ {
setup_type("$_BUF_", {"\\A"}, {"\\Y"}, true);
setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true); setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true);
setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true); setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true);
setup_type("$_NAND_", {"\\A", "\\B"}, {"\\Y"}, true); setup_type("$_NAND_", {"\\A", "\\B"}, {"\\Y"}, true);
@ -261,6 +262,8 @@ struct CellTypes
HANDLE_CELL_TYPE(neg) HANDLE_CELL_TYPE(neg)
#undef HANDLE_CELL_TYPE #undef HANDLE_CELL_TYPE
if (type == "$_BUF_")
return arg1;
if (type == "$_NOT_") if (type == "$_NOT_")
return eval_not(arg1); return eval_not(arg1);
if (type == "$_AND_") if (type == "$_AND_")

1
kernel/rtlil.cc
View file

@ -870,6 +870,7 @@ namespace {
return; return;
} }
if (cell->type == "$_BUF_") { check_gate("AY"); return; }
if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; }
if (cell->type == "$_AND_") { check_gate("ABY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; }
if (cell->type == "$_NAND_") { check_gate("ABY"); return; } if (cell->type == "$_NAND_") { check_gate("ABY"); return; }

10
passes/abc/abc.cc
View file

@ -59,6 +59,7 @@ PRIVATE_NAMESPACE_BEGIN
enum class gate_type_t { enum class gate_type_t {
G_NONE, G_NONE,
G_FF, G_FF,
G_BUF,
G_NOT, G_NOT,
G_AND, G_AND,
G_NAND, G_NAND,
@ -160,7 +161,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
return; return;
} }
if (cell->type == "$_NOT_") if (cell->type.in("$_BUF_", "$_NOT_"))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort("\\Y");
@ -168,7 +169,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
assign_map.apply(sig_a); assign_map.apply(sig_a);
assign_map.apply(sig_y); assign_map.apply(sig_y);
map_signal(sig_y, G(NOT), map_signal(sig_a)); map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a));
module->remove(cell); module->remove(cell);
return; return;
@ -645,7 +646,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
int count_gates = 0; int count_gates = 0;
for (auto &si : signal_list) { for (auto &si : signal_list) {
if (si.type == G(NOT)) { if (si.type == G(BUF)) {
fprintf(f, ".names n%d n%d\n", si.in1, si.id);
fprintf(f, "1 1\n");
} else if (si.type == G(NOT)) {
fprintf(f, ".names n%d n%d\n", si.in1, si.id); fprintf(f, ".names n%d n%d\n", si.in1, si.id);
fprintf(f, "0 1\n"); fprintf(f, "0 1\n");
} else if (si.type == G(AND)) { } else if (si.type == G(AND)) {

4
passes/opt/opt_clean.cc
View file

@ -295,8 +295,8 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
std::vector<RTLIL::Cell*> delcells; std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == "$pos") { if (cell->type.in("$pos", "$_BUF_")) {
bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool();
RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec a = cell->getPort("\\A");
RTLIL::SigSpec y = cell->getPort("\\Y"); RTLIL::SigSpec y = cell->getPort("\\Y");
a.extend_u0(SIZE(y), is_signed); a.extend_u0(SIZE(y), is_signed);

6
techlibs/common/simcells.v
View file

@ -25,6 +25,12 @@
* *
*/ */
module \$_BUF_ (A, Y);
input A;
output Y;
assign Y = A;
endmodule
module \$_NOT_ (A, Y); module \$_NOT_ (A, Y);
input A; input A;
output Y; output Y;