Fix test cases.

passes/techmap/csa_tree.cc

@@ -213,8 +213,7 @@ struct Rewriter {
 		return false;
 	}
 
-	std::vector<Operand> extract_chain_operands(const pool<Cell *> &chain, Cell *root, const dict<Cell *, Cell *> &parent_of,
+	std::vector<Operand> extract_chain_operands(const pool<Cell *> &chain, Cell *root, const dict<Cell *, Cell *> &parent_of, int &neg_compensation)
-						    int &neg_compensation)
 	{
 		pool<SigBit> chain_bits = internal_bits(chain);
 

tests/csa_tree/csa_tree_add_chains.ys

@@ -60,18 +60,22 @@ select -assert-count 14 t:$fa
 select -assert-count 1 t:$add
 design -reset
 
-read_verilog <<EOT
+read_verilog -icells <<EOT
 module alu_add3(
 	input [7:0] a, b, c,
 	output [7:0] y
 );
-	assign y = a + b + c;
+	wire [7:0] tmp, x1, x2, co1, co2;
+	// a + b
+	$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
+		alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp), .X(x1), .CO(co1));
+	// tmp + c
+	$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
+		alu2 (.A(tmp), .B(c), .BI(1'b0), .CI(1'b0), .Y(y), .X(x2), .CO(co2));
 endmodule
 EOT
 hierarchy -auto-top
-proc
+select -assert-count 2 t:$alu
-alumacc
-opt_clean
 csa_tree
 opt_clean
 select -assert-count 1 t:$fa
@@ -79,18 +83,25 @@ select -assert-count 1 t:$add
 select -assert-none t:$alu
 design -reset
 
-read_verilog <<EOT
+read_verilog -icells <<EOT
 module alu_add4(
 	input [7:0] a, b, c, d,
 	output [7:0] y
 );
-	assign y = a + b + c + d;
+	wire [7:0] tmp1, tmp2, x1, x2, x3, co1, co2, co3;
+	// a + b
+	$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
+		alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
+	// c + d
+	$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
+		alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
+	// tmp1 + tmp2
+	$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
+		alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(y), .X(x3), .CO(co3));
 endmodule
 EOT
 hierarchy -auto-top
-proc
+select -assert-count 3 t:$alu
-alumacc
-opt_clean
 csa_tree
 opt_clean
 select -assert-count 2 t:$fa
@@ -98,18 +109,28 @@ select -assert-count 1 t:$add
 select -assert-none t:$alu
 design -reset
 
-read_verilog <<EOT
+read_verilog -icells <<EOT
 module alu_add5(
 	input [11:0] a, b, c, d, e,
 	output [11:0] y
 );
-	assign y = a + b + c + d + e;
+	wire [11:0] tmp1, tmp2, tmp3, x1, x2, x3, x4, co1, co2, co3, co4;
+	// a + b
+	$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
+		alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
+	// c + d
+	$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
+		alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
+	// tmp1 + tmp2
+	$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
+		alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(tmp3), .X(x3), .CO(co3));
+	// tmp3 + e
+	$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
+		alu4 (.A(tmp3), .B(e), .BI(1'b0), .CI(1'b0), .Y(y), .X(x4), .CO(co4));
 endmodule
 EOT
 hierarchy -auto-top
-proc
+select -assert-count 4 t:$alu
-alumacc
-opt_clean
 csa_tree
 opt_clean
 select -assert-count 3 t:$fa
@@ -117,46 +138,7 @@ select -assert-count 1 t:$add
 select -assert-none t:$alu
 design -reset
 
-read_verilog <<EOT
+# Test $macc cells (alumacc+opt output)
-module alu_add8(
-	input [15:0] a, b, c, d, e, f, g, h,
-	output [15:0] y
-);
-	assign y = a + b + c + d + e + f + g + h;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-csa_tree
-opt_clean
-select -assert-count 6 t:$fa
-select -assert-count 1 t:$add
-select -assert-none t:$alu
-design -reset
-
-read_verilog <<EOT
-module alu_add16(
-	input [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
-	input [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
-	output [15:0] y
-);
-	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
-	+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-csa_tree
-opt_clean
-select -assert-count 14 t:$fa
-select -assert-count 1 t:$add
-select -assert-none t:$alu
-design -reset
-
 read_verilog <<EOT
 module macc_add3(
 	input [7:0] a, b, c,
@@ -176,25 +158,6 @@ select -assert-count 1 t:$add
 select -assert-none t:$macc t:$macc_v2 %u
 design -reset
 
-read_verilog <<EOT
-module macc_add4(
-	input [7:0] a, b, c, d,
-	output [7:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt
-csa_tree
-opt_clean
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-select -assert-none t:$macc t:$macc_v2 %u
-design -reset
-
 read_verilog <<EOT
 module macc_add5(
 	input [11:0] a, b, c, d, e,

tests/csa_tree/csa_tree_alu_macc_equiv.ys

@@ -1,111 +1,3 @@
-read_verilog <<EOT
-module equiv_alu_add3(
-	input [3:0] a, b, c,
-	output [3:0] y
-);
-	assign y = a + b + c;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 1 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
-read_verilog <<EOT
-module equiv_alu_add4(
-	input [3:0] a, b, c, d,
-	output [3:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
-read_verilog <<EOT
-module equiv_alu_add8(
-	input [3:0] a, b, c, d, e, f, g, h,
-	output [3:0] y
-);
-	assign y = a + b + c + d + e + f + g + h;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 6 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
-read_verilog <<EOT
-module equiv_alu_signed(
-	input signed [3:0] a, b, c, d,
-	output signed [5:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-count 2 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
-read_verilog <<EOT
-module equiv_alu_sub_mixed(
-	input [3:0] a, b, c, d,
-	output [3:0] y
-);
-	assign y = a + b - c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-min 1 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
-read_verilog <<EOT
-module equiv_alu_sub_all(
-	input [3:0] a, b, c, d,
-	output [3:0] y
-);
-	assign y = a - b - c - d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-alumacc
-opt_clean
-equiv_opt csa_tree
-design -load postopt
-select -assert-min 1 t:$fa
-select -assert-count 1 t:$add
-design -reset
-
 read_verilog <<EOT
 module equiv_macc_add3(
 	input [3:0] a, b, c,
@@ -195,3 +87,21 @@ design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
+
+read_verilog <<EOT
+module equiv_macc_sub_all(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a - b - c - d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt csa_tree
+design -load postopt
+select -assert-min 1 t:$fa
+select -assert-count 1 t:$add
+design -reset

tests/csa_tree/csa_tree_edge_cases.ys

@@ -259,7 +259,7 @@ select -assert-none t:$fa
 design -reset
 
 read_verilog <<EOT
-module alu_mixed_width(
+module macc_mixed_width(
 	input [7:0] a,
 	input [3:0] b,
 	input [15:0] c,
@@ -282,7 +282,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_signed(
+module macc_signed(
 	input signed [7:0] a, b, c, d,
 	output signed [9:0] y
 );
@@ -302,7 +302,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module fir_4tap_alu(
+module fir_4tap_macc(
 	input clk,
 	input [15:0] x, c0, c1, c2, c3,
 	output reg [31:0] y
@@ -328,7 +328,7 @@ select -assert-min 1 t:$dff
 design -reset
 
 read_verilog <<EOT
-module alu_mixed_sign(
+module macc_mixed_sign(
 	input signed [7:0] a,
 	input [7:0] b,
 	input signed [7:0] c,
@@ -350,7 +350,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_wide32(
+module macc_wide32(
 	input [31:0] a, b, c, d,
 	output [31:0] y
 );
@@ -370,7 +370,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_single(
+module passthrough(
 	input [7:0] a,
 	output [7:0] y
 );

tests/csa_tree/csa_tree_idempotent.ys

@@ -20,7 +20,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_idempotent(
+module macc_idempotent(
 	input [15:0] a, b, c, d, e, f, g, h,
 	output [15:0] y
 );

tests/csa_tree/csa_tree_sub_chains.ys

@@ -102,7 +102,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_sub_3op(
+module macc_sub_3op(
 	input [7:0] a, b, c,
 	output [7:0] y
 );
@@ -122,7 +122,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_sub_mixed(
+module macc_sub_mixed2(
 	input [7:0] a, b, c, d,
 	output [7:0] y
 );
@@ -142,7 +142,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_sub_all(
+module macc_sub_all(
 	input [7:0] a, b, c, d,
 	output [7:0] y
 );
@@ -162,7 +162,7 @@ select -assert-none t:$sub
 design -reset
 
 read_verilog <<EOT
-module alu_sub_signed(
+module macc_sub_signed(
 	input signed [7:0] a, b, c, d,
 	output signed [9:0] y
 );