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Fix test cases.

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nella 2026-04-01 18:40:51 +02:00 • committed by nella
parent 135812ab02
commit c3c577f333
6 changed files with 67 additions and 195 deletions
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8
tests/csa_tree/csa_tree_sub_chains.ys
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@ -102,7 +102,7 @@ select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_3op(
module macc_sub_3op(
input [7:0] a, b, c,
output [7:0] y
);
@ -122,7 +122,7 @@ select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_mixed(
module macc_sub_mixed2(
input [7:0] a, b, c, d,
output [7:0] y
);
@ -142,7 +142,7 @@ select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_all(
module macc_sub_all(
input [7:0] a, b, c, d,
output [7:0] y
);
@ -162,7 +162,7 @@ select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_signed(
module macc_sub_signed(
input signed [7:0] a, b, c, d,
output signed [9:0] y
);