mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

fmt: %t/$time support

Browse source
This commit is contained in:
Charlotte 2023-06-28 11:51:20 +10:00 • committed by Marcelina Kościelnicka
parent 52dc397a50
commit c382d7d3ac
7 changed files with 133 additions and 26 deletions
Download patch file Download diff file Expand all files Collapse all files

6
backends/verilog/verilog_backend.cc
View file

@ -1797,6 +1797,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_sigspec(f, arg.sig);
f << ")";
break;
case VerilogFmtArg::TIME:
if (arg.realtime)
f << "$realtime";
else
f << "$time";
break;
default: log_abort();
}
}