mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-18 20:03:39 +00:00
Code Activity

Update doc

Browse source
This commit is contained in:
Eddie Hung 2019-08-19 09:59:57 -07:00
parent d81a090d89
commit c36fca86f7
1 changed files with 4 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
README.md
View file

@ -417,9 +417,10 @@ Verilog Attributes and non-standard features
port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
as a combinatorial loop. as a combinatorial loop.
- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark - The port attribute ``abc_carry`` marks the carry-in (if an input port) and
the carry-in and carry-out ports of a box. This information is necessary for carry-out (if output port) ports of a box. This information is necessary for
`abc9` to preserve the integrity of carry-chains. `abc9` to preserve the integrity of carry-chains. Specifying this attribute
onto a bus port will affect its most significant bit.
Non-standard or SystemVerilog features for formal verification Non-standard or SystemVerilog features for formal verification