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https://github.com/YosysHQ/yosys
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Fix AIGER back-end for multiple symbols per input/latch/output/property
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05df3dbee4
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@ -484,6 +484,8 @@ struct AigerWriter
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if (symbols_mode)
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if (symbols_mode)
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{
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{
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dict<string, vector<string>> symbols;
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for (auto wire : module->wires())
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for (auto wire : module->wires())
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{
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{
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if (wire->name[0] == '$')
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if (wire->name[0] == '$')
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@ -500,38 +502,48 @@ struct AigerWriter
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int a = aig_map.at(sig[i]);
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int a = aig_map.at(sig[i]);
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log_assert((a & 1) == 0);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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if (GetSize(wire) != 1)
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f << stringf("i%d %s[%d]\n", (a >> 1)-1, log_id(wire), i);
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
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else
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else
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f << stringf("i%d %s\n", (a >> 1)-1, log_id(wire));
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
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}
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}
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if (wire->port_output) {
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if (wire->port_output) {
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int o = ordered_outputs.at(sig[i]);
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int o = ordered_outputs.at(sig[i]);
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if (GetSize(wire) != 1)
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if (GetSize(wire) != 1)
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f << stringf("%c%d %s[%d]\n", miter_mode ? 'b' : 'o', o, log_id(wire), i);
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
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else
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else
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f << stringf("%c%d %s\n", miter_mode ? 'b' : 'o', o, log_id(wire));
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
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}
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}
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if (init_inputs.count(sig[i])) {
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if (init_inputs.count(sig[i])) {
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int a = init_inputs.at(sig[i]);
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int a = init_inputs.at(sig[i]);
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log_assert((a & 1) == 0);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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if (GetSize(wire) != 1)
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f << stringf("i%d init:%s[%d]\n", (a >> 1)-1, log_id(wire), i);
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
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else
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else
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f << stringf("i%d init:%s\n", (a >> 1)-1, log_id(wire));
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symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
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}
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}
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if (ordered_latches.count(sig[i])) {
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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int l = ordered_latches.at(sig[i]);
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const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
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const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
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if (GetSize(wire) != 1)
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if (GetSize(wire) != 1)
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f << stringf("l%d %s%s[%d]\n", l, p, log_id(wire), i);
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symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
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else
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else
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f << stringf("l%d %s%s\n", l, p, log_id(wire));
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symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
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}
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}
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}
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}
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}
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}
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symbols.sort();
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for (auto &sym : symbols) {
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f << sym.first;
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std::sort(sym.second.begin(), sym.second.end());
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for (auto &s : sym.second)
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f << " " << s;
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f << std::endl;
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}
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}
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}
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f << stringf("c\nGenerated by %s\n", yosys_version_str);
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f << stringf("c\nGenerated by %s\n", yosys_version_str);
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