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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2024-07-22 17:39:27 +02:00
parent 5a53212bc0
commit c35dd4ab42
1 changed files with 27 additions and 8 deletions
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35
kernel/rtlil.h
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@ -75,10 +75,17 @@ namespace RTLIL
struct Binding; struct Binding;
#ifdef _YOSYS_VAY_ #ifdef _YOSYS_VAY_
struct CoarseCell; // same as Cell in a NOVAY build struct CoarseDynamicCelll; // same as Cell in a NOVAY build
struct FineCell; // only single-bit ports and no parameters struct FineDynamicCell; // only single-bit ports and no parameters
struct AYFineCell; // cell with single-bit ports "A" and "Y" and no parameters
struct ABYFineCell; // cell with single-bit ports "A", "B", and "Y" and no parameters // maybe instead:
// #define X(classname) struct classname;
// #include "kernel/dyncells.xh"
// #uindef X
struct CoarseStaticCell_AwYw; // cell with multi-bit "A" and "B" ports "A_WIDTH" and "Y_WIDTH" parameters
struct CoarseStaticCell_wABSY; // cell with multi-bit "A", "B", and "S" ports and "WIDTH" parameters
struct FineStaticCell_AY; // cell with single-bit ports "A" and "Y" and no parameters
struct FineStaticCell_ABY; // cell with single-bit ports "A", "B", and "Y" and no parameters
// ... // ...
#endif #endif
@ -1600,7 +1607,7 @@ public:
std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const = 0; std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const = 0;
}; };
struct RTLIL::CoarseCell final : public RTLIL::Cell struct RTLIL::CoarseDynamicCelll final : public RTLIL::Cell
{ {
#endif #endif
unsigned int hashidx_; unsigned int hashidx_;
@ -1651,8 +1658,9 @@ struct RTLIL::CoarseCell final : public RTLIL::Cell
std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const; std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const;
}; };
// maybe this will be #include "kernel/dyncells.h", generated by "kernel/dyncells.py"
#ifdef _YOSYS_VAY_ #ifdef _YOSYS_VAY_
struct RTLIL::FineCell final : public RTLIL::Cell struct RTLIL::FineDynamicCell final : public RTLIL::Cell
{ {
dict<RTLIL::IdString, RTLIL::SigBit> connections_; dict<RTLIL::IdString, RTLIL::SigBit> connections_;
@ -1663,7 +1671,7 @@ struct RTLIL::FineCell final : public RTLIL::Cell
std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const; std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const;
}; };
struct RTLIL::AYFineCell final : public RTLIL::Cell struct RTLIL::FineStaticCell_AY final : public RTLIL::Cell
{ {
SigBit portA_, portY_; SigBit portA_, portY_;
@ -1682,7 +1690,7 @@ struct RTLIL::AYFineCell final : public RTLIL::Cell
std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const; std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const;
}; };
struct RTLIL::ABYFineCell final : public RTLIL::Cell struct RTLIL::FineStaticCell_ABY final : public RTLIL::Cell
{ {
SigBit portA_, portB_, portY_; SigBit portA_, portB_, portY_;
@ -1703,6 +1711,17 @@ struct RTLIL::ABYFineCell final : public RTLIL::Cell
}; };
//... //...
#else // _YOSYS_VAY_
struct RTLIL::CoarseDynamicCell final : public RTLIL::Cell {};
struct RTLIL::FineDynamicCell final : public RTLIL::Cell {};
struct RTLIL::CoarseStaticCell_AwYw final : public RTLIL::Cell {};
struct RTLIL::CoarseStaticCell_wABSY final : public RTLIL::Cell {};
struct RTLIL::FineStaticCell_AY final : public RTLIL::Cell {};
struct RTLIL::FineStaticCell_ABY final : public RTLIL::Cell {};
#endif #endif
struct RTLIL::CaseRule : public RTLIL::AttrObject struct RTLIL::CaseRule : public RTLIL::AttrObject