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	assert feature
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					 1 changed files with 40 additions and 9 deletions
				
			
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			@ -96,13 +96,16 @@ struct BtorDumper
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		}
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		curr_cell.clear();
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		cell_type_translation = { 
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					//assert
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					{"$assert","root"},					
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					//unary
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					{"$not","not"},{"$neg","neg"},{"$reduce_and","redand"},
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					{"$reduce_or","redor"},{"$reduce_xor","redxor"},{"$reduce_bool","redor"},
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					//binary
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					{"$and","and"},{"$or","or"},{"$xor","xor"},{"$xnor","xnor"},
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					{"$shr","srl"},{"$shl","sll"},{"$sshr","sra"},{"$sshl","sll"},
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					{"$lt","ult"},{"$le","ulte"},{"$eq","eq"},{"$ne","ne"},{"$gt","ugt"},{"$ge","ugte"},
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					{"$lt","ult"},{"$le","ulte"},{"$gt","ugt"},{"$ge","ugte"},
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					{"$eq","eq"},{"$eqx","eq"},{"$ne","ne"},{"$nex","ne"},
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					{"$add","add"},{"$sub","sub"},{"$mul","mul"},{"$mod","urem"},{"$div","udiv"},
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					//mux
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					{"$mux","cond"},
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			@ -365,6 +368,31 @@ struct BtorDumper
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		if(it==std::end(line_ref))
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		{
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			curr_cell = cell->name;
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			//assert cell
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			if(cell->type == "$assert")
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			{
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				log("writing assert cell - %s\n", cstr(cell->type));
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				const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
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				const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
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				assert(expr->width == 1);
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				assert(en->width == 1);
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				int expr_line = dump_sigspec(expr, 1);
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				int en_line = dump_sigspec(en, 1);
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				int one_line = ++line_num;
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				str = stringf("%d one 1", line_num);
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				fprintf(f, "%s\n", str.c_str());
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				++line_num;
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				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at("$eq").c_str(), 1, en_line, one_line);
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				fprintf(f, "%s\n", str.c_str());
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				++line_num;
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				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 1, line_num-1,
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					expr_line, one_line);
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				fprintf(f, "%s\n", str.c_str());
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				int cell_line = ++line_num;
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				str = stringf("%d %s %d %d", line_num, cell_type_translation.at("$assert").c_str(), 1, line_num-1);
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				fprintf(f, "%s\n", str.c_str());
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				line_ref[cell->name]=cell_line;
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			}
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			//unary cells
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			if(cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos" || cell->type == "$reduce_and" ||
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				cell->type == "$reduce_or" || cell->type == "$reduce_xor" || cell->type == "$reduce_bool")
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			@ -417,12 +445,13 @@ struct BtorDumper
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			}
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			//binary cells
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			else if(cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
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				 cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || 
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				 cell->type == "$ne" || cell->type == "$ge" || cell->type == "$gt" )
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				 cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || 
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				 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt" )
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			{
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				log("writing binary cell - %s\n", cstr(cell->type));
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				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
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				assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$ge" || cell->type == "$gt") || output_width == 1);
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				assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
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					cell->type == "$ge" || cell->type == "$gt") || output_width == 1);
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				bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
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				bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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			@ -439,7 +468,8 @@ struct BtorDumper
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				++line_num;
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				std::string op = cell_type_translation.at(cell->type);
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				if(cell->type == "$lt" || cell->type == "$le" ||
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				 cell->type == "$eq" || cell->type == "$ne" || cell->type == "$ge" || cell->type == "$gt")
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				 cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
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				 cell->type == "$ge" || cell->type == "$gt")
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				{
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					if(l1_signed)
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						op = s_cell_type_translation.at(cell->type);
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			@ -717,7 +747,7 @@ struct BtorDumper
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		{
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			output_sig = &cell->connections.at(RTLIL::IdString("\\DATA"));
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		}
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		else if(cell->type == "$memwr")
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		else if(cell->type == "$memwr" || cell->type == "$assert")
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		{
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			//no output
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		}
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			@ -884,8 +914,9 @@ struct BtorBackend : public Backend {
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					top_module_name = mod_it.first;
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		fprintf(f, "; Generated by %s\n", yosys_version_str);
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		fprintf(f, "; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu>\n");
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		fprintf(f, ";  at Fondazione Bruno Kessler, Trento, Italy\n");
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		fprintf(f, ";  %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
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		fprintf(f, "; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n");
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		fprintf(f, ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n");
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		std::vector<RTLIL::Module*> mod_list;
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