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Make tests/aiger less chatty

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-06-19 12:20:35 +02:00
parent b3441935b1
commit c330379870
1 changed files with 6 additions and 4 deletions
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10
tests/aiger/run-test.sh
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@ -10,8 +10,9 @@ for aag in *.aag; do
# Since ABC cannot read *.aag, read the *.aig instead # Since ABC cannot read *.aag, read the *.aig instead
# (which would have been created by the reference aig2aig utility, # (which would have been created by the reference aig2aig utility,
# available from http://fmv.jku.at/aiger/) # available from http://fmv.jku.at/aiger/)
../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" echo "Checking $aag."
../../yosys -p " ../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
../../yosys -qp "
read_verilog ${aag%.*}_ref.v read_verilog ${aag%.*}_ref.v
prep prep
design -stash gold design -stash gold
@ -26,8 +27,9 @@ sat -verify -prove-asserts -show-ports -seq 16 miter
done done
for aig in *.aig; do for aig in *.aig; do
../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v" echo "Checking $aig."
../../yosys -p " ../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v"
../../yosys -qp "
read_verilog ${aig%.*}_ref.v read_verilog ${aig%.*}_ref.v
prep prep
design -stash gold design -stash gold