mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-13 10:44:45 +00:00
Code Activity

Selective boolopt

Browse source
This commit is contained in:
Alain Dargelas 2024-11-25 15:08:42 -08:00
parent e9b0f73cb3
commit c32d0a412c
8 changed files with 297 additions and 36 deletions
Download patch file Download diff file Expand all files Collapse all files

14
passes/techmap/techmap.cc
View file

@ -165,6 +165,11 @@ struct TechmapWorker
break;
}
for (auto tpl_cell : tpl->cells())
for (auto attr : cell->attributes) {
tpl_cell->attributes[attr.first] = attr.second;
}
dict<IdString, IdString> memory_renames;
for (auto &it : tpl->memories) {
@ -388,6 +393,9 @@ struct TechmapWorker
c->attributes[attr.first] = attr.second;
c->attributes.erase(ID::reprocess_after);
}
for (auto attr : tpl_cell->attributes) {
c->attributes[attr.first] = attr.second;
}
}
for (auto &it : tpl->connections()) {
@ -527,9 +535,9 @@ struct TechmapWorker
{
extmapper_module = extmapper_design->addModule(m_name);
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
extmapper_cell->set_src_attribute(cell->get_src_attribute());
for (auto attr : cell->attributes) {
extmapper_cell->attributes[attr.first] = attr.second;
}
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));