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Selective boolopt

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This commit is contained in:
Alain Dargelas 2024-11-25 15:08:42 -08:00
parent e9b0f73cb3
commit c32d0a412c
8 changed files with 297 additions and 36 deletions
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41
passes/techmap/simplemap.cc
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@ -36,7 +36,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_NOT_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
}
@ -73,7 +73,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, gate_type); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::Y, sig_y[i]);
@ -124,7 +124,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::Cell *gate = module->addCell(NEW_ID2, gate_type); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
@ -137,7 +137,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID2_SUFFIX("sig_t")); // SILIMATE: Improve the naming
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_NOT_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
last_output_cell = gate;
@ -165,7 +165,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
}
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_OR_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
@ -194,7 +194,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_NOT_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
}
@ -223,7 +223,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID2, gate_type); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
gate->setPort(ID::Y, sig_y);
@ -239,19 +239,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec xor_out = module->addWire(NEW_ID2_SUFFIX("xor_out"), max(GetSize(sig_a), GetSize(sig_b))); // SILIMATE: Improve the naming
RTLIL::Cell *xor_cell = module->addXor(NEW_ID2, sig_a, sig_b, xor_out, is_signed, cell->get_src_attribute()); // SILIMATE: Improve the naming
xor_cell->attributes[ID::src] = cell->attributes[ID::src];
xor_cell->attributes = cell->attributes;
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID2_SUFFIX("reduce_out")); // SILIMATE: Improve the naming
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), xor_out, reduce_out, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
reduce_cell->attributes = cell->attributes;
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID2_SUFFIX("not"), reduce_out, sig_y, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
not_cell->attributes[ID::src] = cell->attributes[ID::src];
not_cell->attributes = cell->attributes;
simplemap_lognot(module, not_cell);
module->remove(not_cell);
}
@ -265,7 +265,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::S, cell->getPort(ID::S));
@ -282,7 +282,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::S, sig_s[i]);
@ -298,7 +298,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_TBUF_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::E, sig_e);
gate->setPort(ID::Y, sig_y[i]);
@ -316,7 +316,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
gate->setPort(ID::S, sel[idx]);
@ -339,7 +339,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
SigSpec new_lut_data = module->addWire(NEW_ID2_SUFFIX("data"), GetSize(lut_data)/2); // SILIMATE: Improve the naming
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID2, ID($_MUX_)); // SILIMATE: Improve the naming
gate->attributes[ID::src] = cell->attributes[ID::src];
gate->attributes = cell->attributes;
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
gate->setPort(ID::S, lut_ctrl[idx]);
@ -374,11 +374,16 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
pat.append(State::S1);
}
}
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID2_SUFFIX("eq"), in, pat, false, cell->get_src_attribute()) : State::S1); // SILIMATE: Improve the naming
SigSpec eq_y = module->addWire(NEW_ID2_SUFFIX("eq_out"), max(GetSize(in), GetSize(pat))); // SILIMATE: Improve the naming
Cell* eq = module->addEq(NEW_ID2_SUFFIX("eq"), in, pat, eq_y, false, cell->get_src_attribute());
eq->attributes = cell->attributes;
products.append(GetSize(in) > 0 ? eq_y : State::S1); // SILIMATE: Improve the naming
}
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID2_SUFFIX("reduce_or"), products, false, cell->get_src_attribute())); // SILIMATE: Improve the naming
SigSpec red_or_y = module->addWire(NEW_ID2_SUFFIX("red_or_out"), GetSize(products)); // SILIMATE: Improve the naming
Cell* red_or = module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), products, red_or_y, false, cell->get_src_attribute());
red_or->attributes = cell->attributes;
module->connect(cell->getPort(ID::Y), red_or_y); // SILIMATE: Improve the naming
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)