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Selective boolopt

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This commit is contained in:
Alain Dargelas 2024-11-25 15:08:42 -08:00
parent e9b0f73cb3
commit c32d0a412c
8 changed files with 297 additions and 36 deletions
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6
passes/techmap/aigmap.cc
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@ -110,6 +110,8 @@ struct AigmapPass : public Pass {
if (nand_mode && node.inverter) {
bit = module->addWire(NEW_ID2_SUFFIX("bit"));
auto gate = module->addNandGate(NEW_ID2_SUFFIX("nand"), A, B, bit);
for (auto attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
if (select_mode)
new_sel.insert(gate->name);
@ -121,6 +123,8 @@ struct AigmapPass : public Pass {
else {
bit = module->addWire(NEW_ID2_SUFFIX("bit"));
auto gate = module->addAndGate(NEW_ID2_SUFFIX("and"), A, B, bit);
for (auto attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
if (select_mode)
new_sel.insert(gate->name);
}
@ -130,6 +134,8 @@ struct AigmapPass : public Pass {
if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID2_SUFFIX("new_bit"));
auto gate = module->addNotGate(NEW_ID2_SUFFIX("inv"), bit, new_bit);
for (auto attr : cell->attributes)
gate->attributes[attr.first] = attr.second;
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);