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Merge pull request #1976 from YosysHQ/dave/fix-sim-const

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sim: Fix handling of constant-connected cell inputs at startup
This commit is contained in:
Claire Wolf 2020-04-22 16:57:34 +02:00 • committed by GitHub
commit c32b4bded5
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2 changed files with 18 additions and 1 deletions
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6
passes/sat/sim.cc
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@ -128,8 +128,12 @@ struct SimInstance
for (auto &port : cell->connections()) {
if (cell->input(port.first))
for (auto bit : sigmap(port.second))
for (auto bit : sigmap(port.second)) {
upd_cells[bit].insert(cell);
// Make sure cell inputs connected to constants are updated in the first cycle
if (bit.wire == nullptr)
dirty_bits.insert(bit);
}
}
if (cell->type.in(ID($dff))) {

13
tests/various/sim_const.ys Normal file
View file

@ -0,0 +1,13 @@
read_verilog <<EOT
module top(input clk, output reg [1:0] q);
wire [1:0] x = 2'b10;
always @(posedge clk)
q <= x & 2'b11;
endmodule
EOT
proc
sim -clock clk -n 1 -w top
select -assert-count 1 a:init=2'b10 top/q %i