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Add test

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This commit is contained in:
Eddie Hung 2019-06-10 16:16:26 -07:00
parent a91ea6612a
commit c314ca3c51
2 changed files with 53 additions and 0 deletions
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tests/various/shregmap.ys Normal file
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read_verilog shregmap.v
design -copy-to model $__SHREG_DFF_P_
hierarchy -top shregmap_test
prep
design -save gold
techmap
shregmap -init
opt
stat
# show -width
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__SHREG_DFF_P_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
design -load gate
stat