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Add more Liberty tests and fix parentheses in functions

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This commit is contained in:
Akash Levy 2024-11-05 10:34:51 -08:00
parent 4a5e33520b
commit c2f95d1b5a
7 changed files with 208 additions and 2 deletions
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15
tests/liberty/parenfunc.lib.verilogsim.ok Normal file
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module latch (D, G, Q, QN);
reg IQ, IQN;
input D;
input G;
output Q;
assign Q = IQ; // IQ
output QN;
assign QN = IQN; // IQN
always @* begin
if ((G)) begin
IQ <= D;
IQN <= ~(D);
end
end
endmodule