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Use $__ABC_FF_ instead of $_FF_

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This commit is contained in:
Eddie Hung 2019-06-15 18:16:14 -07:00
parent c04921c3a8
commit c2f3f116d0
3 changed files with 33 additions and 17 deletions
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4
backends/aiger/xaiger.cc
View file

@ -222,8 +222,8 @@ struct XAigerWriter
log_assert(!holes_mode);
// FIXME: Should short here, rather than provide $_DFF_[NP]_
// to ABC as a user cell
// FIXME: Should short here, rather than provide $__ABC_FF_
// to ABC like a user cell
//if (cell->type.in("$_FF_" /*, "$_DFF_N_", "$_DFF_P_"*/))
//{
// SigBit D = sigmap(cell->getPort("\\D").as_bit());

34
passes/techmap/abc9.cc
View file

@ -399,6 +399,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
// count_gates, GetSize(signal_list), count_input, count_output);
#if 0
Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str()));
#endif
Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
std::string buffer;
@ -513,25 +516,22 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// in preparation for stitching mapped_mod in
// Short $_FF_ cells used by ABC (FIXME)
dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
std::vector<RTLIL::Cell*> abc_dff;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
RTLIL::Cell* cell = it->second;
if (cell->type.in("$_AND_", "$_NOT_")) {
it = module->cells_.erase(it);
continue;
}
else if (cell->type.in("$_FF_")) {
RTLIL::Wire *D = cell->getPort("\\D").as_wire();
RTLIL::Wire *Q = cell->getPort("\\Q").as_wire();
Q->attributes.swap(D->attributes);
module->connect(Q, D);
it = module->cells_.erase(it);
continue;
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id")) {
erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
it = module->cells_.erase(it);
continue;
if (cell->type.in("$__ABC_FF_"))
abc_dff.emplace_back(cell);
else {
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id")) {
erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));
it = module->cells_.erase(it);
continue;
}
}
++it;
}
@ -671,6 +671,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module
// TODO: iterate using ports
for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second;
if (!w->port_input && !w->port_output)
@ -697,6 +698,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
for (auto cell : abc_dff) {
RTLIL::SigBit D = cell->getPort("\\D");
RTLIL::SigBit Q = cell->getPort("\\Q");
module->connect(Q, D);
module->remove(cell);
}
//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
log("ABC RESULTS: input signals: %8d\n", in_wires);
log("ABC RESULTS: output signals: %8d\n", out_wires);

12
techlibs/xilinx/ff_map.v
View file

@ -29,12 +29,20 @@ module \$_DFF_P_ (input D, C, output Q);
`else
wire Q_next;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
\$_FF_ abc_dff (.D(Q_next), .Q(Q));
\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
`endif
endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q);
`ifndef _ABC
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
`else
wire Q_next;
\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0));
\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
`endif
endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule