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Moved all tests in arch sub directory

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This commit is contained in:
Miodrag Milanovic 2019-10-18 11:06:12 +02:00
parent 3c41599ee1
commit c2ec7ca703
151 changed files with 5 additions and 5 deletions
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tests/arch/xilinx/counter.ys Normal file
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read_verilog counter.v
hierarchy -top top
proc
flatten
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDCE
select -assert-count 1 t:LUT1
select -assert-count 7 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D