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Moved all tests in arch sub directory
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151 changed files with 5 additions and 5 deletions
17
tests/arch/xilinx/counter.v
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17
tests/arch/xilinx/counter.v
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module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset) begin
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out <= 8'b0 ;
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end else
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out <= out + 1;
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endmodule
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