mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 15:24:57 +00:00
Code Activity

Moved all tests in arch sub directory

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-18 11:06:12 +02:00
parent 3c41599ee1
commit c2ec7ca703
151 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

33
tests/arch/efinix/latches.ys Normal file
View file

@ -0,0 +1,33 @@
read_verilog latches.v
design -save read
hierarchy -top latchp
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D