mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-11 21:50:54 +00:00
Moved all tests in arch sub directory
This commit is contained in:
parent
3c41599ee1
commit
c2ec7ca703
151 changed files with 5 additions and 5 deletions
12
tests/arch/efinix/counter.ys
Normal file
12
tests/arch/efinix/counter.ys
Normal file
|
@ -0,0 +1,12 @@
|
|||
read_verilog counter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:EFX_GBUFCE
|
||||
select -assert-count 8 t:EFX_FF
|
||||
select -assert-count 9 t:EFX_ADD
|
||||
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D
|
Loading…
Add table
Add a link
Reference in a new issue