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Moved all tests in arch sub directory

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This commit is contained in:
Miodrag Milanovic 2019-10-18 11:06:12 +02:00
parent 3c41599ee1
commit c2ec7ca703
151 changed files with 5 additions and 5 deletions
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tests/arch/ecp5/mux.ys Normal file
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read_verilog mux.v
design -save read
hierarchy -top mux2
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
select -assert-none t:LUT4 %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:L6MUX21
select -assert-count 4 t:LUT4
select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:L6MUX21
select -assert-count 7 t:LUT4
select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 8 t:L6MUX21
select -assert-count 26 t:LUT4
select -assert-count 12 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D