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Moved all tests in arch sub directory
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151 changed files with 5 additions and 5 deletions
20
tests/arch/anlogic/dffs.ys
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20
tests/arch/anlogic/dffs.ys
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read_verilog dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_SEQ %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:AL_MAP_LUT3
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select -assert-count 1 t:AL_MAP_SEQ
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select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
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