mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Fix bug in write_smt2 (export logic driving hierarchical cells before exporting regs)

Browse source
This commit is contained in:
Clifford Wolf 2017-08-25 11:44:48 +02:00
parent d3b3dd8e88
commit c2d737457a
1 changed files with 34 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

68
backends/smt2/smt2.cc
View file

@ -794,6 +794,40 @@ struct Smt2Worker
}
}
if (verbose) log("=> export logic driving hierarchical cells\n");
for (auto cell : module->cells())
if (module->design->module(cell->type) != nullptr)
export_cell(cell);
while (!hiercells_queue.empty())
{
std::set<RTLIL::Cell*> queue;
queue.swap(hiercells_queue);
for (auto cell : queue)
{
string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
Module *m = module->design->module(cell->type);
log_assert(m != nullptr);
for (auto &conn : cell->connections())
{
Wire *w = m->wire(conn.first);
SigSpec sig = sigmap(conn.second);
if (bvmode || GetSize(w) == 1) {
hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
} else {
for (int i = 0; i < GetSize(w); i++)
hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
}
}
}
}
for (int iter = 1; !registers.empty(); iter++)
{
pool<Cell*> this_regs;
@ -940,40 +974,6 @@ struct Smt2Worker
}
}
if (verbose) log("=> export logic driving hierarchical cells\n");
for (auto cell : module->cells())
if (module->design->module(cell->type) != nullptr)
export_cell(cell);
while (!hiercells_queue.empty())
{
std::set<RTLIL::Cell*> queue;
queue.swap(hiercells_queue);
for (auto cell : queue)
{
string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
Module *m = module->design->module(cell->type);
log_assert(m != nullptr);
for (auto &conn : cell->connections())
{
Wire *w = m->wire(conn.first);
SigSpec sig = sigmap(conn.second);
if (bvmode || GetSize(w) == 1) {
hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
} else {
for (int i = 0; i < GetSize(w); i++)
hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
}
}
}
}
if (verbose) log("=> finalizing SMT2 representation of %s.\n", log_id(module));
for (auto c : hiercells) {