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Merge 9fcb15213e into 9d0cdb8551

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nataliakokoromyti 2026-05-23 13:09:47 +08:00 • committed by GitHub
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3 changed files with 31 additions and 1 deletions
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12
passes/equiv/equiv_make.cc
View file

@ -34,6 +34,7 @@ struct EquivMakeWorker
vector<string> blacklists; vector<string> blacklists;
vector<string> encfiles; vector<string> encfiles;
bool make_assert; bool make_assert;
bool nocells;
pool<IdString> blacklist_names; pool<IdString> blacklist_names;
dict<IdString, dict<Const, Const>> encdata; dict<IdString, dict<Const, Const>> encdata;
@ -420,7 +421,8 @@ struct EquivMakeWorker
copy_to_equiv(); copy_to_equiv();
find_undriven_nets(false); find_undriven_nets(false);
find_same_wires(); find_same_wires();
find_same_cells(); if (!nocells)
find_same_cells();
find_undriven_nets(true); find_undriven_nets(true);
} }
}; };
@ -451,6 +453,9 @@ struct EquivMakePass : public Pass {
log(" Check equivalence with $assert cells instead of $equiv.\n"); log(" Check equivalence with $assert cells instead of $equiv.\n");
log(" $eqx (===) is used to compare signals."); log(" $eqx (===) is used to compare signals.");
log("\n"); log("\n");
log(" -nocells\n");
log(" Do not check for equivalent cells, just wires.\n");
log("\n");
log("Note: The circuit created by this command is not a miter (with something like\n"); log("Note: The circuit created by this command is not a miter (with something like\n");
log("a trigger output), but instead uses $equiv cells to encode the equivalence\n"); log("a trigger output), but instead uses $equiv cells to encode the equivalence\n");
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
@ -462,6 +467,7 @@ struct EquivMakePass : public Pass {
worker.ct.setup(design); worker.ct.setup(design);
worker.inames = false; worker.inames = false;
worker.make_assert = false; worker.make_assert = false;
worker.nocells = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -482,6 +488,10 @@ struct EquivMakePass : public Pass {
worker.make_assert = true; worker.make_assert = true;
continue; continue;
} }
if (args[argidx] == "-nocells") {
worker.nocells = true;
continue;
}
break; break;
} }

7
passes/equiv/equiv_opt.cc
View file

@ -60,6 +60,9 @@ struct EquivOptPass:public ScriptPass
log(" -undef\n"); log(" -undef\n");
log(" enable modelling of undef states during equiv_induct.\n"); log(" enable modelling of undef states during equiv_induct.\n");
log("\n"); log("\n");
log(" -nocells\n");
log(" Do not check for equivalent cells, just wires.\n");
log("\n");
log(" -nocheck\n"); log(" -nocheck\n");
log(" disable running check before and after the command under test.\n"); log(" disable running check before and after the command under test.\n");
log("\n"); log("\n");
@ -126,6 +129,10 @@ struct EquivOptPass:public ScriptPass
async2sync = true; async2sync = true;
continue; continue;
} }
if (args[argidx] == "-nocells") {
make_opts += " -nocells";
continue;
}
break; break;
} }

13
tests/various/equiv_nocells.ys Normal file
View file

@ -0,0 +1,13 @@
read_verilog <<EOT
module gold(input a, input b, output y);
assign y = a & b;
endmodule
module gate(input a, input b, output y);
assign y = a & b;
endmodule
EOT
equiv_make -nocells gold gate equiv
equiv_simple equiv
equiv_status -assert equiv