mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

anlogic: support BRAM mapping

Browse source 
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng 2021-12-17 20:25:32 +08:00
parent 60c3ea367c
commit c2b7ad3b28
8 changed files with 283 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

13
tests/arch/anlogic/blockram.ys Normal file
View file

@ -0,0 +1,13 @@
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sp
proc
memory -nomap
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
memory
opt -full
design -load postopt
cd sync_ram_sp
select -assert-count 1 t:EG_PHY_BRAM
select -assert-none t:EG_PHY_BRAM %% t:* %D

2
tests/arch/anlogic/lutram.ys
View file

@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram
memory
opt -full