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https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
This commit is contained in:
Eddie Hung
commit
c28bea0382
22 changed files with 1075 additions and 1153 deletions
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@ -78,11 +78,11 @@ struct XAigerWriter
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Module *module;
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SigMap sigmap;
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pool<SigBit> input_bits, output_bits;
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pool<SigBit> input_bits, output_bits, external_bits;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<SigBit> ci_bits, co_bits;
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dict<SigBit, std::pair<int,int>> ff_bits;
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dict<SigBit, Cell*> ff_bits;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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@ -93,6 +93,7 @@ struct XAigerWriter
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dict<SigBit, int> ordered_outputs;
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vector<Cell*> box_list;
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dict<IdString, std::vector<IdString>> box_ports;
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int mkgate(int a0, int a1)
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{
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@ -140,7 +141,6 @@ struct XAigerWriter
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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pool<SigBit> inout_bits;
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// promote public wires
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for (auto wire : module->wires())
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@ -157,7 +157,12 @@ struct XAigerWriter
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if (wire->get_bool_attribute(ID::keep))
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sigmap.add(wire);
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for (auto wire : module->wires())
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// First, collect all the ports in port_id order
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// since module->wires() could be sorted
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// alphabetically
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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log_assert(wire);
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wirebit(wire, i);
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@ -171,9 +176,6 @@ struct XAigerWriter
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continue;
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}
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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if (wire->port_input)
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input_bits.insert(bit);
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@ -182,9 +184,19 @@ struct XAigerWriter
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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}
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}
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if (wire->port_input && wire->port_output)
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inout_bits.insert(wirebit);
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for (auto wire : module->wires())
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wirebit(wire, i);
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SigBit bit = sigmap(wirebit);
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if (bit.wire) {
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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}
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}
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// TODO: Speed up toposort -- ultimately we care about
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@ -192,7 +204,6 @@ struct XAigerWriter
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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std::vector<Cell*> flop_boxes;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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@ -224,25 +235,44 @@ struct XAigerWriter
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continue;
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}
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if (cell->type == "$__ABC9_FF_")
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if (cell->type == "$__ABC9_FF_" &&
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// The presence of an abc9_mergeability attribute indicates
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// that we do want to pass this flop to ABC
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cell->attributes.count("\\abc9_mergeability"))
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{
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SigBit D = sigmap(cell->getPort("\\D").as_bit());
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SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, 2)));
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auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
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log_assert(r.second);
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continue;
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}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module) {
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bool abc9_box = inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep");
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bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
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bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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if (abc9_box && cell->get_bool_attribute("\\abc9_keep"))
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abc9_box = false;
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (abc9_box) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_input && !port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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if (!abc9_flop)
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continue;
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}
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if (port_wire->port_output) {
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int arrival = 0;
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auto it = port_wire->attributes.find("\\abc9_arrival");
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@ -255,27 +285,13 @@ struct XAigerWriter
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for (auto bit : sigmap(conn.second))
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arrival_times[bit] = arrival;
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}
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if (abc9_box) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_input && !port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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if (abc9_box) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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if (inst_module->attributes.count("\\abc9_flop"))
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flop_boxes.push_back(cell);
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continue;
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}
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if (abc9_box) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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continue;
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}
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}
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bool cell_known = inst_module || cell->known();
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@ -298,76 +314,12 @@ struct XAigerWriter
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output_bits.insert(b);
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}
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}
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if (is_output)
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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input_bits.insert(O);
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}
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}
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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if (abc9_box_seen) {
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dict<IdString, std::pair<IdString,int>> flop_q;
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for (auto cell : flop_boxes) {
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auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
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SigBit d;
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if (r.second) {
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for (const auto &conn : cell->connections()) {
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const SigSpec &rhs = conn.second;
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if (!rhs.is_bit())
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continue;
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if (!ff_bits.count(rhs))
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continue;
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r.first->second.first = conn.first;
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Module *inst_module = module->design->module(cell->type);
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Wire *wire = inst_module->wire(conn.first);
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log_assert(wire);
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auto jt = wire->attributes.find("\\abc9_arrival");
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if (jt != wire->attributes.end()) {
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if (jt->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.second = jt->second.as_int();
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}
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d = rhs;
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log_assert(d == sigmap(d));
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break;
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}
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}
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else
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d = cell->getPort(r.first->second.first);
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auto &rhs = ff_bits.at(d);
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auto it = cell->attributes.find(ID(abc9_mergeability));
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log_assert(it != cell->attributes.end());
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rhs.first = it->second.as_int();
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cell->attributes.erase(it);
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it = cell->attributes.find(ID(abc9_init));
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log_assert(it != cell->attributes.end());
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log_assert(GetSize(it->second) == 1);
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if (it->second[0] == State::S1)
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rhs.second = 1;
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else if (it->second[0] == State::S0)
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rhs.second = 0;
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else {
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log_assert(it->second[0] == State::Sx);
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rhs.second = 0;
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}
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cell->attributes.erase(it);
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auto arrival = r.first->second.second;
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if (arrival)
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arrival_times[d] = arrival;
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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@ -396,18 +348,49 @@ struct XAigerWriter
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log_assert(cell);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id")
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|| cell->get_bool_attribute("\\abc9_keep"))
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire* w = box_module->wire(port_name);
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for (auto port_name : r.first->second) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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auto it = cell->connections_.find(port_name);
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if (w->port_input) {
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@ -422,7 +405,7 @@ struct XAigerWriter
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cell->setPort(port_name, rhs);
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}
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for (auto b : rhs.bits()) {
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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@ -453,21 +436,20 @@ struct XAigerWriter
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}
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for (const auto &b : rhs.bits()) {
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ci_bits.emplace_back(b);
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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input_bits.erase(O);
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ci_bits.emplace_back(b);
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undriven_bits.erase(O);
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}
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}
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}
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// Connect <cell>.$abc9_currQ (inserted by abc9_map.v) as an input to the flop box
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// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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SigSpec rhs = module->wire(stringf("%s.$abc9_currQ", cell->name.c_str()));
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SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.$abc9_currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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@ -496,62 +478,54 @@ struct XAigerWriter
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unused_bits.erase(sigmap(bit));
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for (auto bit : unused_bits)
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undriven_bits.erase(bit);
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if (!undriven_bits.empty()) {
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for (auto bit : undriven_bits) {
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log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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input_bits.insert(bit);
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}
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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}
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struct sort_by_port_id {
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bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
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return a.wire->port_id < b.wire->port_id;
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}
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};
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input_bits.sort(sort_by_port_id());
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output_bits.sort(sort_by_port_id());
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not_map.sort();
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and_map.sort();
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// Make all undriven bits a primary input
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for (auto bit : undriven_bits) {
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input_bits.insert(bit);
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undriven_bits.erase(bit);
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}
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aig_map[State::S0] = 0;
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aig_map[State::S1] = 1;
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for (auto bit : input_bits) {
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// pool<> iterates in LIFO order...
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for (int i = input_bits.size()-1; i >= 0; i--) {
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const auto &bit = *input_bits.element(i);
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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for (const auto &i : ff_bits) {
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const SigBit &bit = i.first;
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const Cell *cell = i.second;
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const SigBit &q = sigmap(cell->getPort("\\Q"));
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aig_m++, aig_i++;
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log_assert(!aig_map.count(q));
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aig_map[q] = 2*aig_m;
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}
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for (auto &bit : ci_bits) {
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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dict<SigBit, int> ff_aig_map;
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for (auto &bit : ci_bits) {
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aig_m++, aig_i++;
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auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
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if (!r.second)
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ff_aig_map[bit] = 2*aig_m;
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}
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for (auto bit : co_bits) {
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ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto bit : output_bits) {
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// pool<> iterates in LIFO order...
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for (int i = output_bits.size()-1; i >= 0; i--) {
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const auto &bit = *output_bits.element(i);
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ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto &i : ff_bits) {
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const SigBit &bit = i.first;
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const SigBit &d = i.first;
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aig_o++;
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aig_outputs.push_back(ff_aig_map.at(bit));
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aig_outputs.push_back(aig_map.at(d));
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}
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}
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@ -653,9 +627,7 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(derived_name);
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int box_inputs = 0, box_outputs = 0;
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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for (const auto &port_name : box_module->ports) {
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for (auto port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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if (w->port_input)
|
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|
|
@ -664,8 +636,7 @@ struct XAigerWriter
|
|||
box_outputs += GetSize(w);
|
||||
}
|
||||
|
||||
// For flops only, create an extra 1-bit input that drives a new wire
|
||||
// called "<cell>.$abc9_currQ" that is used below
|
||||
// For flops only, create an extra 1-bit input for abc9_ff.Q
|
||||
if (box_module->get_bool_attribute("\\abc9_flop"))
|
||||
box_inputs++;
|
||||
|
||||
|
|
@ -685,13 +656,25 @@ struct XAigerWriter
|
|||
write_s_buffer(ff_bits.size());
|
||||
|
||||
for (const auto &i : ff_bits) {
|
||||
const SigBit &bit = i.first;
|
||||
int mergeability = i.second.first;
|
||||
const SigBit &d = i.first;
|
||||
const Cell *cell = i.second;
|
||||
|
||||
int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
|
||||
log_assert(mergeability > 0);
|
||||
write_r_buffer(mergeability);
|
||||
int init = i.second.second;
|
||||
write_s_buffer(init);
|
||||
write_i_buffer(arrival_times.at(bit, 0));
|
||||
|
||||
Const init = cell->attributes.at(ID(abc9_init));
|
||||
log_assert(GetSize(init) == 1);
|
||||
if (init == State::S1)
|
||||
write_s_buffer(1);
|
||||
else if (init == State::S0)
|
||||
write_s_buffer(0);
|
||||
else {
|
||||
log_assert(init == State::Sx);
|
||||
write_s_buffer(0);
|
||||
}
|
||||
|
||||
write_i_buffer(arrival_times.at(d, 0));
|
||||
//write_o_buffer(0);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue