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fmt: add tests for Verilog round trip of format expressions.

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whitequark 2020-12-06 04:08:44 +00:00 • committed by Marcelina Kościelnicka
parent 67052f62ec
commit c285880684
5 changed files with 95 additions and 2 deletions
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13
tests/fmt/roundtrip_tb.v Normal file
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module tb;
reg clk = 1'b0;
reg [31:0] data;
m dut(.clk(clk), .data(data));
initial begin
data = 32'haa;
#10; clk = 1; #10; clk = 0;
data = 32'haaaa;
#10; clk = 1; #10; clk = 0;
end
endmodule