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fmt: add tests for Verilog round trip of format expressions.

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whitequark 2020-12-06 04:08:44 +00:00 • committed by Marcelina Kościelnicka
parent 67052f62ec
commit c285880684
5 changed files with 95 additions and 2 deletions
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22
tests/fmt/roundtrip.v Normal file
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module m(input clk, input `SIGN [31:0] data);
always @(posedge clk)
// All on a single line to avoid order effects.
`ifdef BASE_DEC
$display(":%d:%-d:%+d:%+-d:%0d:%-0d:%+0d:%+-0d:%20d:%-20d:%+20d:%+-20d:%020d:%-020d:%+020d:%+-020d:",
data, data, data, data, data, data, data, data, data, data, data, data, data, data, data, data);
`endif
`ifdef BASE_HEX
$display(":%h:%-h:%0h:%-0h:%20h:%-20h:%020h:%-020h:",
data, data, data, data, data, data, data, data);
`endif
`ifdef BASE_OCT
$display(":%o:%-o:%0o:%-0o:%20o:%-20o:%020o:%-020o:",
data, data, data, data, data, data, data, data);
`endif
`ifdef BASE_BIN
$display(":%b:%-b:%0b:%-0b:%20b:%-20b:%020b:%-020b:",
data, data, data, data, data, data, data, data);
`endif
endmodule