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fmt: add tests for Verilog round trip of format expressions.

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whitequark 2020-12-06 04:08:44 +00:00 • committed by Marcelina Kościelnicka
parent 67052f62ec
commit c285880684
5 changed files with 95 additions and 2 deletions
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17
tests/fmt/always_display.v Normal file
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module m(input clk, rst, en, input [31:0] data);
`ifdef EVENT_CLK
always @(posedge clk)
`endif
`ifdef EVENT_CLK_RST
always @(posedge clk or negedge rst)
`endif
`ifdef EVENT_STAR
always @(*)
`endif
`ifdef COND_EN
if (en)
`endif
$display("data=%d", data);
endmodule