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Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

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dh73 2017-04-05 23:01:29 -05:00
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techlibs/altera_intel/max10/cells_arith_max10.v Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter LUT = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire tempcombout;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("cin")) _TECHMAP_REPLACE_
( .dataa(AA),
.datab(BB),
.datac(C),
.datad(1'b0),
.cin(C[i]),
.cout(CO[i]),
.combout(Y[i]) );
end: slice
endgenerate
assign X = C;
endmodule

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techlibs/altera_intel/max10/cells_comb_max10.v Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera MAX10 devices Input Buffer Primitive */
module fiftyfivenm_io_ibuf (output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera MAX10 devices Output Buffer Primitive */
module fiftyfivenm_io_obuf (output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera MAX10 4-input non-fracturable LUT Primitive */
module fiftyfivenm_lcell_comb (output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "fiftyfivenm_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // fiftyfivenm_lcell_comb
/* Altera MAX10 D Flip-Flop Primitive */
// TODO: Implement advanced simulation functions
module dffeas ( output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload );
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q;
always @(posedge clk)
q <= d;
endmodule

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techlibs/altera_intel/max10/cells_map_max10.v Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Flip-flop D
module \$_DFF_P_ (input D, input C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule //
// Input buffer map
module \$__inpad (input I, output O);
fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //